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LMK04828: Currently LMK04828 not having EEPROM.

Rajesh khanna
Intellectual 700 points
Part Number: LMK04828

Hi,

We are using LMK04828 for our design for High speed JESD clock generation i.e ref clocks and sysref to FPGA's.

We facing problem when FPGA signals are taken for monitoring purpose, as the clocks are not stable when FPGA is powered on.

same FPGA needs to configure the LMK04828 since we don't have eeprom/flash internal to clocking device, also in current form factor we cannot put any other small device to program the LMK before FPGA powering sequence.

Request TI any plan to incorporate EEPROM in future version of LMK series or we need to modify our design with other parts from other vendor to meet the need.

Regards,

Rajesh khanna

  • 0
    TI__Mastermind 33730 points

    Hi Rajesh,

    Are you using the LMK04828 in dual-loop mode? Usually the VCXO from PLL1 is a stable reference source in this case, and the OSCout port can be used to provide a stable buffered copy of OSCin on startup. Also, normally the DCLKout/SDCLKout pins will self-oscillate at a stable frequency (typical value provided in the datasheet) due to the internal VCO of PLL2 ramping to maximum supported frequency in the absence of a stable OSCin.

    In theory you could also ensure stability by forcing the CPout2 voltage low on startup - since the charge pump current gain is limited to 3.2mA maximum, the charge pump can be safely shorted to GND with an MOSFET or BJT. Note however that the capacitance of an external device may impact the loop filter capacitance and the loop bandwidth for PLL2.

    At this time, there are no plans to include EEPROM on LMK04828 or similar dual-loop jitter cleaner products.

    Regards,