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LMK04832: Setup and Hold Times in distribution mode

Izik
Expert 1585 points
Part Number: LMK04832

Hello 

I would like to use the LMK04832 in distribution mode, to transfer high frequency clock (~3GHz) and sysref to DAC. The high frequency clock enters the LMK using CLKin1 input.  

Looking on figure 6 on LMK04832 datasheet, it looks like the signal CLKin0 which is used to reset the dividers and generate SYSREF, is actually sampled by the divided signal using the D-flip flop. 

So basically I don't need anymore to meet the stringent requirement of the SU and Hold time of the ~3GHz clock, but the much more relaxed timing of the divided signal, up to 8191 division value. 

Is that correct?

Thanks

  • 0
    TI__Mastermind 33790 points

    Hello Izik,

    When operating the SYSREF_MUX using the divider reclocking flip flop, the CLKin0 (or SYNC pin) input can be reclocked to the output of the divider, which you correctly inferred has much more relaxed setup and hold requirements. The phase of the SYSREF divider relative to other clocks can be controlled by setting the digital delay values for the clock output dividers and the SYSREF divider, then generating a divider SYNC event.

    It's worth noting that the initial SYNC event which sets digital delays and aligns clocks to each other usually does not have stringent timing requirements, because all clocks can interrupted and aligned by the SYNC event. In most cases, aligning all outputs of the device is sufficient; the exact moment when the synchronization occurs is usually not important, since SYSREF can thereafter be used to establish a known timing across the system. There are some exceptions, such as when the phase of the input must be aligned to the phase of the output (which comes up more often in multi-device synchronization tasks).

    Additionally, if generating the SYSREF event does not have some external timing requirement, you could consider using the SYSREF pulser instead through SYNC pin or SPI. The SYSREF pulser is also clocked to the output of the SYSREF divider, and can generate 1/2/4/8 pulses after receiving a single SYSREF event request.

    If I understood correctly, you are trying to distribute 3GHz to the DAC directly through LMK04832. The LMK04832 includes two options for passing input to output: divide-by-1, and high performance bypass. The choice trades performance for increased control over timing.

    • Divide-by-1 mode uses the divider+digital delay blocks, and both output clock and SYSREF edges should be synchronous. Aligning SYSREF to device clock in this case is achieved simply by setting the SYSREF outputs to use the half-step delay. However, CML output format is restricted in this mode, and cannot be used on even-numbered outputs (0, 2, ..., 12), which limits output swing and noise floor performance.
    • Bypass mode bypasses the divider, delay, and other internal muxes to directly output from the clock distribution path. Even-numbered outputs must use CML output format when bypassed, in exchange for higher output swing and improved noise floor. However, the SYSREF phase may not be aligned precisely with the device clocks, due to the difference in propagation delay and lack of retiming at the SYSREF output. Some experimentation with a high-frequency oscilloscope and the SYSREF_ADLY register settings may be needed to properly align the SYSREF divider output with the bypassed device clock falling edge.

    Regards,

  • 0 in reply to Derek Payne
    Expert 1585 points

    Hello Derek and thank you for the answer.

    I want to elaborate more on my mode of work - we actually have multiple Dacs and lmk's on our system, and all of them must have deterministic phase difference between their output clocks, with respect to the input clkin0 strobe. This event may occur several times during operation, each time the same deterministic latency is required.

    Is it possible to achieve using the path described on figure 6?

    Thanks

    Izik

  • 0 in reply to Izik
    TI__Mastermind 33790 points

    Hello Izik,

    There are many ways to ensure multi-device synchronization as described. CLKin0 reclocked through SYSREF is a valid option, assuming you have some way to align the phase of the SYSREF dividers across all the devices. Of course, then the challenge is making sure that all the different device SYSREF dividers begin counting at the same instant...

    If you can start the LMK04832, synchronize (reset) all the dividers, and then start the 3GHz distribution clock, this trivially ensures the devices begin counting at the same cycle. But if you must synchronize while the 3GHz clocks are running, you will need to meet the setup and hold time requirements for the clock distribution frequency (no greater than one-half cycle for each). Fortunately you should only have to synchronize once. After the synchronization event, you should be able to rely on the SYSREF reclocking or the pulser to guarantee deterministic latency from some triggering event.

    Regards,

  • 0 in reply to Derek Payne
    Expert 1585 points

    Basically delay between devices is not a problem if it is constant - our system calibrates the delay once and the calibration values need to be correct for all sync events. The 3GHz reference must be active since some of the LMK outputs are the either the input clock itself or its divisions, all must have constant phase. 

    We also use the sysref to change the DAC NCO value - another event which must be deterministic since the NCO resets its phase on each frequency change. 

    Is there a way to achieve this and still avoiding the timing requirements of the 3GHz clock setup and hold? 

    Thanks again

  • 0 in reply to Izik
    TI__Mastermind 33790 points

    The delay between the SYSREF divider edges of different parts on power-up is not repeatable, especially after programming the device. So at some point, the SYSREF dividers of all devices must still be aligned, and the setup and hold constraints of the high frequency clock will still apply.

    In some ways, meeting the setup and hold constraints of the high frequency clock is not as challenging as it initially sounds. Consider the case where a master LMK04832 drives several slave LMK04832 devices, and the slaves are configured in distribution mode (master configuration, it turns out, is unimportant). The master LMK04832 can be synchronized without any critical timing, since it just distributes high frequency clocks and SYNC pulses/SYSREF requests. And after synchronization, the master LMK04832 has extremely consistent digital and analog delay adjustments available on the SYNC/SYSREF output, so each SYNC pulse can be precisely timed to the edge of its companion high frequency clock. If the high frequency clock and the SYNC/SYSREF clock lengths to each individual device are matched, achieving the needed setup and hold times is trivial; the paths to each device and the variations in propagation delay over temperature need not be matched to each other device, since this is a "constant" delay and will be calibrated out. And this scheme is deterministic independent of the depth of the clock tree. Once the SYSREF divider edge position in each device is positioned at a deterministic point with respect to the master device, SYNC and SYSREF events can be retimed to the SYSREF divider in each device and the setup and hold time for SYNC and SYSREF events is expanded to a SYSREF clock period. But once a scheme for synchronizing against the high frequency clock is established, the value of reclocking SYNC and SYSREF events to the SYSREF divider seems marginal at best. In fact, it may make more sense to exclusively handle SYSREF timing in the master device, and operate all slave devices as repeaters with one extra cycle of SYSREF delay.

    If a PLL is included in the loop, multi-device synchronization becomes much simpler. Some examples of the possible configurations are given in:

    However, if the VCO performance of the LMK04832 is worse than the input clock, sacrificing performance to achieve determinism is an undesirable solution.

    A final (untested) thought: if your SYSREF divider is less than 1024, theoretically you could activate PLL1, send the SYSREF frequency to CLKin0 as a reference input to the PLL1 phase detector, configure the feedback mux to supply the SYSREF divider output as the feedback input to the PLL1 phase detector, and use TRACK_EN to activate the PLL1 phase detector 10-bit ADC and read back the phase error of the SYSREF divider with respect to the SYNC pulse. Then you could use dynamic digital delay to tune the phase of the SYSREF divider manually until the phase is where you want it and record the ADC reading. Now, no matter what state or phase alignment the SYSREF divider starts at in any device, as long as you have the correct ADC reading to position the SYSREF divider in the right spot, you can use dynamic digital delay to recalibrate the SYSREF divider phase until you see the correct ADC reading. Again I stress that this is untested, so I have no idea how it would work over temperature or if the 10-bit ADC value is linear enough to use for this kind of calibration.

    Regards,