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LMK04828: continuous SYSREF

Kazuhiko Hirano
Genius 14968 points
Part Number: LMK04828

Hello,

 

My customer would like to use continuous SYSREF to establish JESD204B link between an FPGA and TI ADC/DAC.

After establishing the JESD204B link, they would like to disable the continuous SYSREF to prevent undesired crosstalk.

 

Q1:

To enable the continuous SYSREF, just datasheet table1 register settings are required and SYNC/SYSREF pin signal is not required?

 

Q2:

To disable the continuous SYSREF, what register settings are required?

 

Q3:

The continuous SYSREF to TI ADC/DAC should be dc-coupled or ac-coupled?

 

Best regards,

 

K.Hirano

  • 0
    TI__Mastermind 33510 points

    Hello Hirano-san,

    Q1:
    There are two ways to enable continuous SYSREF given in Table 1:

    • Use the "Continuous SYSREF" configuration - just follow register settings, no external SYNC signal required
    • Use the "External SYSREF Request" configuration - external signal required on SYNC pin (polarity MUX is bypassed)

    Q2:
    Disabling continuous SYSREF requires different settings for different modes.

    • "Continuous SYSREF" - Set SYSREF_MUX to 0, 1, or 2
    • "External SYSREF Request" - Deassert the signal on the SYNC pin (bring to logic low).

    Also, we recommend disabling the ADC/DAC SYSREF receiver before disabling the LMK04828 SYSREF whenever possible, to prevent unintended side effects from runt pulses. 

    Q3:
    If possible, we recommend DC-coupled. Confirm that the VOH and VOL levels of the chosen output format correspond with the input levels required by the TI ADC/DAC. Some ADC/DAC with 3.3V or 2.5V I/O can directly accept LVDS from LMK04828. Other ADC/DAC use 1.8V digital I/O levels which are not usually compatible with DC-coupled LVDS. For 1.8V systems, LCPECL may be more appropriate.

    If the DC-coupled I/O levels are not compatible, AC-coupling is acceptable when the ADC/DAC SYSREF receiver can be enabled/disabled. Please keep in mind that AC-coupling creates a high-pass filter, so low frequency edges may be impacted. With 0.1µF coupling capacitors into 100Ω differential load, the filter corner is 1/(2*pi*50*1e-7) = about 32kHz. In almost all cases the SYSREF frequency is greater than the corner frequency of the filter, so the SYSREF edges will still be reliably detected by the ADC/DAC. But at frequencies below 100x corner frequency (<3.2MHz), the Vpp voltage will be greater than the nominal signal amplitude due to the coupling capacitor DC bias that accumulates after each edge, which may violate ADC/DAC I/O minimum and maximum voltage requirements.

    If you are still unsure about AC- or DC-coupling, consult the ADC/DAC team through E2E regarding their specific device.

    Regards,