Hi all
Would you mind if we ask LMK05318?
There is the description Table8 on the data sheet.
And there is the description on the datasheet also.
"A SYNC event can be asserted by the hardware GPIO0/SYNCN pin (active low) or the SYNC_SW register bit (active high)."
We assume that SYNC event can be asserted by the hardware GPIO0/SYNCN pin (active low) or the SYNC_SW register bit.
Therefore, is it possble to enable SYNC event with following conditons?
GPIO/SYNC PIN SYNC_SW BIT
0 X
X 1
In these case, will "OUTPUT DIVIDER AND DRIVER STATE" be "Output driver(s) muted and output divider(s) reset"?
Kind regards,
Hirotaka Matsumoto