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LMK04828: SYSREF to device clock alignment

Kazuhiko Hirano
Genius 15408 points
Part Number: LMK04828


Hello,

 

My customer would like to generate two SYSREF pulses at either “JESD204B pulser on pin transition” or “JESD204B pulser on SPI programming” in the datasheet table 1.

In both cases, does the two SYSREF pulse output always have deterministic fixed phase relationship to DCLKoutX at every SYNC event?

Then, customer can adjust delay to get enough tsetup and thold based on this deterministic phase relation?

 

Best regards,

 

K.Hirano

  • 0
    TI__Mastermind 33860 points

    Hello Hirano-san,

    The SYSREF pulse output will always have deterministic phase relationship to DCLKoutX, but they may not have a fixed phase relationship to DCLKoutX.

    If VCO frequency is 3000MHz, DCLKoutX is 100MHz (divider = 30), and SYSREF is 10MHz (100MHz/10, SYSREF_DIV = 300), the SYSREF pulser output will always have both deterministic and fixed phase relationship to DCLKoutX. This is because the greatest common divisor, GCD(100MHz, 10MHz) = 10MHz. In other words, when the SYSREF frequency is the greatest common divisor of all device clocks, the SYSREF output will always have a deterministic and fixed phase relationship to all of the DCLKoutX outputs.

    If VCO frequency is 3000MHz, DCLKoutX is 100MHz (divider = 30), and SYSREF is 12MHz (SYSREF_DIV = 250), the SYSREF pulser output will have a deterministic phase relationship to DCLKoutX, but the phase relationship will not be fixed. This is because the greatest common divisor, GCD(100MHz, 12MHz) = 4MHz. Since GCD(100MHz, 12MHz) = 12MHz / 3, there are three possible phase relationships between the 12MHz clock and the 100MHz clock. In other words, when the SYSREF frequency is not the greatest common divisor of all device clocks, the SYSREF output will have a deterministic phase relationship to all device clocks (there will still be a limited number of predictable phases between device clocks and SYSREF), but not a fixed phase relationship to all device clocks.

    The customer should ensure that the SYSREF frequency is equal to the greatest common divisor of the device clock frequencies, so that the SYSREF to device clock phase relationship is always deterministic and fixed. Then, the customer can adjust the digital delays to get enough Tsetup and Thold based on this deterministic and fixed phase relationship.

    Also, if the customer has some device clocks that do not need to have a deterministic and fixed phase relationship to the SYSREF, like some FPGA state machine clock or asynchronous memory clock, they do not need to be considered in the greatest common divisor calculation. Only clocks that must be synchronous with the JESD clocks need to be considered in the GCD calculation.

    Regards,