LMK1C1102: 3.3V input clock when VDD = 1.8V

franziskus

Part Number: LMK1C1102
Other Parts Discussed in Thread: LMK1C1104

Team,

is it possible to have a 3.3V clock on V_CLKIN when VDD is 1.8V?
The 3.3V tolerant input is only mentioned in the feature list of the datasheet and in the abs max ratings.

My customer needs a clock buffer with two outputs (1.8V) that can handle 3.3V input CLKin.

Thanks!

over 3 years ago

0 Lane Boyd over 3 years ago

TI__Genius 16845 points

Yes, that is OK. I would anticipate duty cycle distortion for 3.3V input while powered from 1.8V.

Kind regards,
Lane

0 franziskus over 3 years ago in reply to Lane Boyd

TI__Expert 6766 points

Thanks Lane!

What kind of distortion do you expect?

Is there a better fitting device in our portfolio that you would recommend instead?

0 Lane Boyd over 3 years ago in reply to franziskus

TI__Genius 16845 points

LMK1C1104 is a good recommendation based on the requirement.

The duty cycle distortion will depend on the input clock frequency and edge rate. When supplied from VDD = 1.8V, the input threshold is 900mV. Higher frequency and slower edges will make the duty cycle distortion worse, and vice versa.

Due to the dependence on input condition, it is difficult to guarantee duty cycle distortion in this condition. We do specify the duty cycle as 45% to 55% for a 50% duty cycle input where the clock amplitude matches the supply voltage. I hope this information helps.

Kind regards,
Lane

0 franziskus over 3 years ago in reply to Lane Boyd

TI__Expert 6766 points

Thanks Lane!

Clock & timing

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LMK1C1102: 3.3V input clock when VDD = 1.8V