LMK04228: LMK04228 loop review for low jitter

Jerry Chen

Part Number: LMK04228
Other Parts Discussed in Thread: AFE7769, LMK04828

Hi team,

I'm using LMK04228 to clock AFE7769. Below is my design for filter, charge pump gain, etc. Could you pls help review the PLL1 and PLL2 loop design is fine for low jitter? I would like to minimize the jitter and make sure PLL1 is stable to be locked to 24.576MHz. After that, I will focus on checking the internal PLL design of AFE7769.

The VCXO characteristics of PLL1 are Kvco=4kHz/V and load=15pF.

Thanks.

LMK04828 SYSREF Continuous AF77- improved loop.tcs

PLL1: TI PLLatinum Sim LMK04828B PLL1 design.zip

PLL2: TI PLLatinum Sim LMK04828B PLL2 design.zip

over 5 years ago

0 Derek Payne over 5 years ago

TI__Mastermind 33690 points

Hi Jerry,

PLL1 looks okay, but it's hard to tell without the VCXO metrics. Do you have a datasheet for the VCXO, or at least the phase noise performance of the VCXO at a few offsets e.g. 100Hz, 1kHz, 10MHz?

In the most recent PLLatinum Sim update (just a few weeks ago), we made some updates to LMK04828 (and therefore LMK04228) performance. For example, the Kvco value I predict for PLL2 is 20.8, not 17; consequently my C1 = 0.068 and my R2 = 0.56kΩ, which seems to yield slightly better performance.

Regards,

0 Jerry Chen over 5 years ago in reply to Derek Payne

TI__Expert 5110 points

Thank you, Derek.

You could find the VCXO specs for PLL1.

0 Derek Payne over 5 years ago in reply to Jerry Chen

TI__Mastermind 33690 points

Hi Jerry,

Thanks for supplying the VCXO characteristics. The noise performance on that VCXO is modest (-140dBc/Hz at far-out offsets), so the PLL2 performance is actually completely dominated by PLL1 performance:

I calculate about 300fs jitter 12k-20M at 1228.8MHz using this VCXO.

PLL1 and PLL2 both look stable.

Regards,

Clock & timing

Clock & timing forum

LMK04228: LMK04228 loop review for low jitter