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LMH1983: Register settings for Free-run and genlock

na na78
Guru 16770 points
Part Number: LMH1983
Other Parts Discussed in Thread: LMH1981

Hi

We referenced the Figure 22 in the datasheet as a typical application of genlock mode and designed a custom board.
The timing signals (H/V/F) from LMH1981 are buffered with a FPGA once, then coming to LMH1983.
That because we suppose to select either free-run mode (no input timing signals from FPGA) or genlock mode (with H/V/F signals from FPGA).

Then, we have some questions.

1. When we work LMH1983 as the free-run mode, do we all have to do is setting registers like Table 13?
2. When does NO_LOCK assert in the free-run mode?
3. Is it possible to change the free-run mode to the genlock mode with the same circuit?
4. If answer to question 3 is yes, is it enough to change the register settings from Table 8 to Table 13?
5. If answer to question 3 is yes, is there a recommended sequence to change the register settings for each mode?

BestRegards

  • 0
    TI__Mastermind 18070 points

    Hi there,

    We will get back to you next Monday.

    Regards,
    Hao

  • 0 in reply to Hao Z
    Guru 16770 points

    Hi Hao

    Thank you for your reply.
    I'm looking forward to hearing from you.

    BestRegards
    Hide

  • 0 in reply to na na78
    TI__Expert 6140 points

    Hello, 

    Yes, table 13 is the correct register settings to follow in order to put the device in free run mode. 

    Free-run mode means PLL1 is open loop, which is similar to Genlock mode without any ref input.  So free-run mode should not affect lock time. As PLL1 has the smallest loop bandwidth, the NO_LOCK will assert when PLL1 locks. 

    I'm double checking on switching from free run mode to genlock and will let you know. 

    Thanks and regards, Amin 

  • 0 in reply to Amin Eshraghi
    Guru 16770 points

    Hi Amin

    Thank you for your reply.

    >Free-run mode means PLL1 is open loop, which is similar to Genlock mode without any ref input.  So free-run mode should >not affect lock time. As PLL1 has the smallest loop bandwidth, the NO_LOCK will assert when PLL1 locks. 

    I saw Figure 13 of datasheet.  It shows the timing of NO_LOCK reaction.
    When the loss of reference, NO_LOCK is going to be low (=LOCK?) after 4.4s past.
    Does it mean the device can offer LOCK signal for the user (or external device) to inform LOCK event even in free-run mode?

    >I'm double checking on switching from free run mode to genlock and will let you know. 
    Thank you for your cooperation.  I'm looking forward to your info.

    BestRegards
    na

  • 0 in reply to na na78
    Guru 16770 points

    Hi

    I have additional question for the following description from the datasheet.

    "When a loss of reference occurs during genlock, PLL1 can default to either Free-run or Holdover operation"

    Does it mean that a loss of reference has to be occurred while operating in genlock when the device would be shifted to free-run mode or holdover mode?

    I wonder that the device would work properly if input references are not applied at start-up in genlock mode.

    BestRegards
    na

  • 0 in reply to na na78
    TI__Expert 6140 points

    Hi, 

    Some corrections to my earlier answers. 

    1. Writing Reg 0x05[4:3] is all that is needed to select free-run mode or genlock mode.
    2. NO_LOCK pin should be high when in free-run mode. Since in free-run mode there's no reference signal. 
    3. Even if PLL1 is configured for genlock mode by setting 0x05[4:3] = 01’b, PLL1 will enter free-run mode if there is a loss of reference condition.  PLL1 loop filter can be the same for both modes of operation.
    4. Only Reg 0x05[4:3] are necessary to manually switch between free-run and genlock modes.
    5. No specific sequence since Reg 0x05 is the only register that needs to be written per answer #4.

    Regards, 

    Amin

  • 0 in reply to Amin Eshraghi
    Guru 16770 points

    Hi Amin

    Thank you for your reply.
    I'd like to arrange my question to avoid inconvenience.

    First, my questions 1 to 5 are cleared with your latest answers.
    I understand that the device with the register setting of 0x05[4:3] = 01’b can work in genlock basically and enter to free-run when there is a loss of reference.

    The followings are additional questions.

    6. In your answer 3, you mentioned the NO_LOCK pin should be high when in free-run mode.
    In Figure 3, NO_LOCK goes to low after 4.4s in default settings.
    Does Figure 3 indicate NO_LOCK reaction except for in free-run mode?



    7. You mentioned what we need to select free-run mode or genlock mode is writing reg:0x05[4:3:].
    Does not LOR mode register (0x05[2]) relate for free-run operation at a loss of reference?
    Because the default settings of LOR mode register is 0 (=Holdover on LOR).

    8. If we set 0x05[4:3] = 01'b, PLL1 would be configured as genlock mode.
    I understand that the device would be enter the free-run mode if a loss of reference occurs while genlock operation.
    However, I'm not sure that the device with no references can enter the free-run mode right from the start.
    Could it be possible to enter the free-run in this case?

    BestRegards
    na

  • 0 in reply to na na78
    Guru 16770 points

    I appreciate if you could reply to my questions.

  • 0 in reply to na na78
    TI__Expert 6140 points

    Hello, 

    6. The NO_LOCK is essentially a status pin that operates when in Genlock mode. Since it requires a reference input (and other registers) to be set in order to determine PLL state (lock or not). So for free run, and no reference, it will just remain high.

    7.  LOR mode register determines whether device enters holdover or free run mode when the reference disappears (obviously configured in genlock mode) 

    8. If you are in genlock mode but no reference is available device will either go into holdover or free run. 

    Note holdover operation requires specific setup, review datasheet section 8.4.4

    Thanks and regards,

    Amin

  • 0 in reply to Amin Eshraghi
    Guru 16770 points

    Hi Amin

    Thank you for your reply.

    >6.
    OK. I understood.

    >7
    OK. I understood I should set 0x05[2] =1 to work for free-run when there is a loss of reference.

    >8
    I would like to set to genlock mode but the device would be in default.  
    So, the register 0x05[2] would be '0' which means holdover on LOR.
    According to the description of Holdover mode, in the event that the reference is lost, there is an A/D — D/A pair that is able to take over for the PLL control loop and hold the VCXO control voltage constant.

    However, if the device work with no input reference right from the start, PLL1 would never been locked and D/A could not hold VCXO control voltage.
    So, it seems the holdover mode is not intended a situation that there is no reference right from the start.
    If it is supposed that a situation with no input reference right from the start, I think at least 0x05[2] should be set as 1 (free-run mode).

    Is my understanding correct?

    BestRegards
    na

  • 0 in reply to na na78
    TI__Mastermind 28560 points

    Hello Na,

    In regard to your feedback on question #8; on page 29 of the datasheet, register 0x16 and 0x17 contain the Vc_HOLD value.  The holdover value set by the DAC in holdover mode.  The MSB, 0x16 power on reset value is binary 10.  The LSB in register 0x17 is not defined.  This indicates holdover mode from the start may have been an anticipated case, except I would have liked to see the LSB default as 0x00.  Given what I see in the datasheet, with the LSB being undefined, values could range from 512 to 1023.

    However, as you state - if you want to specifically control the voltage, then 0x05[2] = 1 for free-run mode would allow you to set the voltage more exactly using using registers 0x18 and 0x19.  It defaults to 0x1ff = 511.

    73,
    Timothy

  • 0 in reply to Timothy T
    Guru 16770 points

    Hi Timothy

    Thank you for your reply.

    Could you tell me how to interpret value of 0x18 and 0x19 into as an actual control voltage?
     0x1ff = 511 =>? V

    BestRegards

  • 0 in reply to na na78
    TI__Mastermind 28560 points

    Hello Na,

    The DAC voltage is a 10 bit number, so it is my expectation that programming 0 would be close to 0 V, and 1023 clost to Vdd.  I was not able to confirm.  Note however that the DAC output range is specified 0.5 V off the rails, so I wouldn't expect 0 V or Vdd at the extremes.

    73,
    Timothy

  • 0 in reply to Timothy T
    Guru 16770 points

    Hi  Timothy

    Thank you for your reply.
    I understood.

    BestRegards
    na