LMK04828: Ext VCO - A System Perspective Question

Hi Chris,

LMK0482x has an Integer-N divider because it's simple, and because the targeted use cases in wireless infrastructure, test and measurement, etc. can typically achieve their desired frequency plan without the integer N-divider becoming a limitation.

As far as I'm aware, there's no technology reason preventing SYSREF generation on a fractional N-divider PLL - the LMX2594 includes a JESD204B SYSREF generator, for example. Integer-N isn't strictly speaking a requirement, but orchestrating the SYSREF timing gets more complicated for a fractional device (especially when multiple devices must be synchronized). For example, with an integer N-divider, there's easy opportunities to establish digital delay in terms of VCO cycles, which share a deterministic relationship to the input clock. In multi-device systems, if you can guarantee the input clock arrives at each integer-N PLL at the same time, you also get a reasonable guarantee that the SYSREF pulses will be aligned to the same clock cycle across all devices. With a fractional-N divider, it's much harder to determine the input-to-output phase relationship unless you SYNC every device at precisely the same time. In many cases, the synchronization requirements place limitations on the phase detector frequency and thus the performance, and almost always prevent the use of the R-path multiplier if present.

There's also no concept analogous to "zero-delay mode" for a fractional-N divider. With an integer-N divider, the output path can be included in the feedback loop, and the input-to-output phase relationship can be made deterministic or even reduced to a single possible relationship, trivializing multi-device synchronization requirements. With zero-delay mode guarantees, all system delays can be discretized into multiples of input clock periods, and digital delay blocks can compensate for any system delay mismatches; this reduces calibration burden in multi-device systems considerably, to the point that some applications would be impossible without it. With a fractional-N divider, the only possible solution is synchronizing every device at exactly the same time, and hoping for repeatable and consistent values of the VCO calibration time, analog lock time, etc. Newer devices such as the LMX2820 have made some advances in ensuring the repeatability and predictability of the elapsed time from SYNC edge to known input-to-output phase relationship, so this problem isn't as bad as it has been in the past. But this still only solves the input-to-output phase relationship at t=0, some instant after the SYNC event. With an integer-N divider, the input-to-output phase relationship is fully deterministic at all times, so keeping track of the input clock cycle upon which a SYSREF request must be made for precise device clock to SYSREF counts (again useful for multi-device synchronization) is usually very straightforward. Unlike with an integer-N divider, the input-to-output phase relationship of a fractional-N divider is constantly changing, so generating SYSREF requests aligned to specific device clock cycles becomes a challenge without computational overhead applied to predicting the input-to-output phase relationship before making the SYSREF request. Moreover, the delay from SYSREF requester to clock generator must be well-characterized for every device in the system, or the SYSREF could become misaligned across PVT. And if multiple devices must operate at different fractions with the same input frequency, predicting the phase where the device clocks and SYSREFs all align is a considerable challenge.

I'm not sure I understand your comment about PLL2 PFD rate limitation. Is this driven by performance concerns or by frequency planning limitations? In the case of performance concerns, the LMK04832 is a p2p replacement for the LMK04828, with more than double the maximum PFD rate. As far as frequency planning, I could imagine the constraint of K * LCM(SYSREF, PFD) = VCO as the limitation you're describing, though in some sense this is why the jitter cleaner is a dual-loop device in the first place: when you have some constraining input frequency e.g. 10MHz, and your output clock frequency should be a frequency which shares a very low GCD with the input e.g. 122.88MHz, PLL1 can be operated with a very low phase detector frequency of 80kHz, phase determinism can be preserved throughout the entire system, and PLL2 still achieves reasonable performance with a sufficiently high quality VCXO. 

With the LMK04828 (and the LMK04832), the SYSREF divider is an integer divide of the VCO frequency, but I suppose there's no strict reason why this must be the case. The SYSREF frequency has a defined integer quotient relationship to the device clock, defined by the LMFC configuration of JESD204B-compliant data sources/sinks. But JESD204B from a system perspective doesn't care if the device clocks or the SYSREF are integer divides of a VCO frequency, as long as the device clock/SYSREF relationship is satisfied. In practice, TI JESD204B clock generators and jitter cleaners don't have fractional input/output dividers, fractional multipliers, or any other solution for creating a non-integer relationship between the VCO frequency and the device clocks/SYSREFs as of today.

Ultimately, if it's easier or cheaper to use the LMK04828 as a JESD204B buffer/divider for fanout, and you'd prefer to drive the Fin pins with some flexible frequency synthesizer, then go for it - we see this use case all the time. You could even cascade LMK04828 PLL1 into the input of the synthesizer, then feed the synth output back into CLKin1 for distribution, and use it like a jitter cleaner, if you needed better close-in performance.

Regards,