LMK04828: questions regarding the datasheet

Hi Beni,

First, I appreciate your careful attention to our datasheet, especially bringing the discrepancies to our attention. This is very helpful for us when making datasheet revisions.

1. Your understanding of the note is correct - the PLL should remain locked across the whole operating temperature range. For comparison, consider the LMK04828-EP, which has a wider operating temperature range of -55°C to 105°C while sharing equivalent functionality to the LMK04828 commercial version. In the LMK04828-EP datasheet, the specification is instead a 160°C range.

The motivation behind including this note is to explain when the user must manually trigger a new calibration. Operation outside of the rated temperature is not guaranteed, but speaking practically it is very likely that at some point the PLL operating temperature range could exceed 85°C (and though less likely, could drop below -40°C) and the device may lose lock. Note that in the scenario described, the PLL loss of lock and the operating temperature may be uncorrelated. If the user tries to re-lock at 90°C, and the temperature may afterward drop to < -35°C, the PLL is not guaranteed to stay in lock between -35°C and -40°C until the VCO calibration is run again. In other words, this specification is not designed to limit the operating temperature range, but to suggest corrective action may be required when the operating specs of the device are violated (action required: re-calibrate within the operating specifications).

2. Argh, indeed you have highlighted an error on both counts. Note that the correct values for SDCLKoutY_ADLY are listed in TICS Pro for the condition of SDCLKoutY_ADLY_EN.
a) 0xE ought to be 2250ps and 0xF ought to be 2400ps. Table must be updated.
b) Delay range is 700ps to 3400ps, not 700ps to 2950ps. 

3. Your description of the DCLKoutX_MUX is correct. Figure 12 in the datasheet shows the path associated with each DCLKoutX_MUX option, from 0x0 at the top to 0x3 at the bottom.

4. Three hits and a miss:
a) Correct, DDLYd8_EN is the correct name for this field.
b) Correct, 0x16A[5:0] should read PLL2_DLD_CNT[13:8].
c) Correct, it should read SDCLKoutY_HS instead of DCLKoutX_HS.
d) In this case, incorrect: holdover does cause PLL2 to stay locked on frequency with minimal frequency drift. This is because, when PLL1 reference input is removed, the PLL1 charge pump is tri-stated, and the VCXO is instead driven by a constant voltage corresponding to the last "known good voltage" sampled while PLL1 remained in lock. Since the VCXO control voltage is constant, the VCXO frequency should remain constant, thus ensuring that the reference frequency into PLL2 does not drift too much in any direction. The VCXO will still be subject to voltage or temperature fluctuations, so PLL2 will have some small amount of frequency drift, but compare this to when holdover is not used - the VCXO control voltage will rail to VCC or GND, in most cases drastically pulling PLL2 reference frequency tens or hundreds of PPM from the frequency attained while PLL1 was locked.

Regards,

Thanks!