The 2019 revision of the datasheet shows a divide value of 1 in Table 7-31 yet Functional Block Diagram 1.4 shows only values of 2-8 allowable. I have been using a divide setting of 1 and still getting a divide by 2 as was shown in the previous revision of the datasheet.
Is the new datasheet incorrect? Can the input clock divider actually be set to a implement a divide value of 1 without the explicit bypass circuit?
