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LMK04828: SPI 3-wire read timing

Koichiro Tashiro
Mastermind 22290 points
Part Number: LMK04828
Other Parts Discussed in Thread: LM74

Hi,

I have a question from my customer about SPI 3-wire protocol.
I know there are a lot of threads relating to this subject, but I could not find exact answer to this question.

Suppose read operation is performed by Master device(MCU).
According to Datasheet Figure 1, SDIO pin is switched from input to output just after A12 to A0 are shifted out from Master(MCU).
Then D7 to D0 are shifted out from Slave(LMK04828).

Question) What is exact timing SDIO signal switched from output to input?
(In other word, by when Master side needs to switch MOSI signal to input or HiZ?)
Customer needs this timing to avoid a situation both Master and Slave drive SDIO line at the same time.

As far as I understood, only tdv timing is defined in datasheet, but this value is the maximum delay the valid read data are driven on SDIO line.
There is possibility SDIO is driven by slave before tdv timing.

By the way, I never heard any TI MCUs supporting this 3-wire half-duplex SPI protocol.
(We only support full-duplex 3-wire using SCLK, MOSI, MISO)
Is this commonly used by other manufacturers?

Thanks and regards,
Koichiro Tashiro

  • 0
    TI__Mastermind 18070 points

    Hi Koichiro,

    My coworker will get back to you tomorrow.

    Regards,
    Hao

  • 0
    TI__Mastermind 28550 points

    Hello Koichiro-san,

    Koichiro Tashiro said:
    Question) What is exact timing SDIO signal switched from output to input?

    I'll advise you tomorrow by when I think I can have this information.

    Koichiro Tashiro said:
    By the way, I never heard any TI MCUs supporting this 3-wire half-duplex SPI protocol.
    (We only support full-duplex 3-wire using SCLK, MOSI, MISO)
    Is this commonly used by other manufacturers?

    I am not sure about other manufacturers.  However, when you say full-duplex 3-wire SPI, you mean what I would call 4-wire SPI as there is an additional CS* pin, correct?

    Two other items for you to consider:

    1) Using 4-wire SPI to drive 3-wire SPI interface: Note that you can connect a 4-wire SPI to the a 3-wire half-duplex SPI as illustrated (from LM74 datasheet).  Note that MISO is always a high impedance input, when SDIO (or SI/O as per figure 18 below) becomes an input, then "GPIO2" which is MOSI will then be able to drive the high impedance load of two input pins with a source impedance of 10 kohm.

    2) LMK04828 doesn't require 3-wire SPI for readback.  Any of the pins CLKin_SEL0 (Pin 58), CLKin_SEL1 (Pin 59), Status_LD1 (Pin 31), Status_LD2 (Pin 48), or RESET/GPO (Pin 5), could all be programmed for SPI reset through the xxxx_MUX register through any of the above pins.

    73,
    Timothy

  • 0 in reply to Timothy T
    TI__Mastermind 28550 points

    I'll get you an update on #1 by Wednesday.

    73,
    Timothy

  • 0 in reply to Timothy T
    TI__Mastermind 28550 points

    Hello Koichiro-san,

    The tdv specification would apply to the output driver converting to output.  So within 20 ns of the falling clock edge before the first data read bit.

    73,
    Timothy