LMK04828: device configuration-related questions

Beni Falk

Part Number: LMK04828
Other Parts Discussed in Thread: LMK04821

We are using the LMK04828 in single-loop mode (PLL1 is disabled). Not using zero-delay features. For some applications we use DCLK outputs only while for others we also use SYSREF outputs.

I am writing a software driver that supports several use cases of the device.

All references below are to the LMK0482x datasheet (SNAS605AS –MARCH 2013–REVISED MAY 2020).

I have the following questions:

1. Register initialization sequence in conjunction with SYNC/SYSREF:

a) SYSREF_CLR control - the datasheet says (in section 9.3.2.1.2) that it is asserted automatically on power up (and I presume following a software reset) and that it only needs to be cleared by software. On the other hand, the programming sequence in section 9.3.2.1.1 includes an explicit setting of this bit.

When should software set and reset SYSREF_CLR?

Note: in section 9.3.2.1.2 the datasheet indicates that SYSREF_CLR must be held at 1 for a minimum of 15 VCO cycles. Given that VCO frequency for all parts is always greater than 2 GHz, the above translates to 7.5 ns. Is it theoretically possible to set SYSREF_CLR for 7.5 ns or less? Or perhaps this is related to the fact that need to have VCO locked before pulsing SYSREF_CLR?

b) How is the programming sequence specified in section 9.3.2.1.1 related to the one specified in section 9.5.1?

I presumed that the sequence in section 9.3.2.1.1 includes steps that are needed to support SYSREF functionality beyond the steps that are needed for basic functionality that are specified in section 9.5.1. However there seems to be some overlap between the two. In particular, they both include setting up of DCLKoutx_DDLY_CNTH, DCLKoutx_DDLY_CNTL, DCLKoutx_HS, SDCLKoutY_DDLY. Am I to understand that if using SYSREF these registers need to be programmed twice?

Also, is it necessary to program DCLKoutX_DDLY_CNTH, DCLKoutx_DDLY_CNTL, DCLKoutX_HS and SDCLKoutY_DDLY while SYSREF_CLR is held at 1?

I understand about the need to program SYSREF-related registers twice to first set up for manual sync and subsequently set up the desired SYSREF configuration, however what about the registers mentioned above? Should they also be programmed twice?

Note: I found the following document: e2e.ti.com/.../Key-Points-to-setting-up-SYSREF-on-LMK0482x_5F00_e2e_5F00_2016_2D00_06_2D00_29.pdf and it doesn’t seem to indicate that one needs to program DCLKoutx_DDLY_CNTH, DCLKoutx_DDLY_CNTL, DCLKoutx_HS, SDCLKoutY_DDLY registers twice, nor that it is necessary to program them while SYSREF_CLR is held at 1.

Please advise.

2. Continuous SYSREF on external request:

a) According to Table 1 need to set SYNC_MODE to 0 for this case. I presume that this corresponds to the topmost input to the SYNC_MODE multiplexer in Figure 13. In such case the SYNC input cannot affect SYSREF generation in any way. Is the setting of SYNC_MODE to 0 correct for this case?

b) According to section 9.3.2.2.3 the pulser need not be powered up in this case, however in Table 1 for the external SYSREF request case, it says “Pulser powered on”. Also, in the description of SYSREF_REQ_EN (register 0x16a) it says to enable the pulser when using this feature.

Which is correct?

3. We are using single-loop mode, thus we must use the settings defined in Table 8. On the other hand, we would like to use FB MUX for the sake of routing CLKout6 to OSCout. Is this doable (in single-loop mode)? If yes, I presume that for this we need to set FB_MUX_EN to 1. Am I correct?

4. SDCLK to DCLK synchronization (datasheet section 9.3.4.) – assuming that we desire to synchronize SDCLK and DCLK, and assuming that we want to be able to use the maximum possible span of DCLKout and SDCLKout digital delay values, given Equations 1 and 2 it seems to me that I should set the global SYSREF delay (SDCLK_DDLY) to the smallest possible value in all circumstances. Am I correct?

5. PLL2_DLD_COUNT setting – what are the considerations for setting this value? Can I safely use the default value (8192)? This is what TICS Pro is doing.

6. PLL2 prescaler (PLL2 P):

a) Under what conditions would one set it to any value other than the minimum? To achieve effective N values greater than 262143?

b) The prescaler can be powered down (PLL2_PD in register 0x173). When it is powered down does it mean that it is bypassed (i.e. effective PLL2 N value is PLL2_N x 1)? Is it legitimate to power it down when using PLL2?

Note: I tried powering it down in the TICS Pro software and it didn’t seem to change the prescaler value and VCO frequency.

(Could it be because I am using TICS Pro on my computer and it is not connected to any hardware?)

7. The datasheet mentions DAC in many places. Just for my understanding, what is it? Does it refer to an internal D/A converter which drives the CPout1 pin?

Thanks,

Beni Falk

over 5 years ago

0 Derek Payne over 5 years ago

TI__Mastermind 33970 points

Hi Beni,

...
1. Whenever the SYSREF divider is synchronized, SYSREF_CLR should first be asserted for 15 clock distribution path cycles. POR and reset do assert SYSREF_CLR automatically, so explicitly setting SYSREF_CLR high for 15 clock distribution path cycles is only required if the SYSREF divider must be synchronized more than once per POR/reset. That said, it is easy to write a single synchronization procedure that explicitly sets SYSREF_CLR, waits at least 15 clock distribution path cycles, and deasserts SYSREF_CLR; and there is no penalty for explicitly setting SYSREF_CLR when it is already set (as could be the case after POR/reset).
  
  SYSREF_CLR must be asserted for >15 clock distribution path cycles, which could be the VCO or an external clock/VCO provided on CLKin1. If your application uses the internal VCOs, you could write the SYSREF_CLR=1 and immediately write the SYSREF_CLR=0. But if the clock distribution path is fed externally with e.g. a 1kHz clock, SYSREF_CLR must be asserted for >15ms. In most cases, the >15 clock distribution path cycle requirement is trivially satisfied.
2. Every step up to 2d in 9.3.2.1.1 can be performed as part of the recommended programming sequence in 9.5.1. SYNC_POL, SYNC_MODE, SYSREF_MUX, DCLKoutX_DIV, SYSREF_DIV, SYSREF_PD, SYSREF_DDLY_PD, DCLKoutX_DDLY_CNTL, DCLKoutX_DDLY_CNTH, SYSREF_DDLY, SDCLKoutY_DDLY, DCLKoutX_HS, SDCLKoutY_HS, DCLKoutX_MUX, and all the analog delay settings can be programmed just once during initial programming in 9.5.1.
  
  The synchronization steps from 2e onward are usually performed after 9.5.1 is complete and the PLLs are locked. So there are some registers which get written twice: SYNC_POL, to toggle the SYNC input state; SYNC_DISx, to gate off the SYNC event so that the SYSREF divider output does not reset the device clocks or the SYSREF divider (or in subsequent SYNC events, to allow the SYNC event to reset these dividers); SYSREF_CLR, exclusively to reset the SYSREF_DDLY counter back to 0 any time the SYSREF divider is synchronized; SYNC_MODE and SYSREF_MUX, to choose the SYNC source or to reroute the SYSREF output to the SDCLKoutY outputs.
  
  SYSREF_CLR is only attached to SYSREF_DDLY, SYSREF_PD, and SYSREF_DDLY_PD. As long as SYSREF_PD=0 and SYSREF_DDLY_PD=0, SYSREF_CLR state can be programmed at any time (except for the SYSREF_DDLY clock cycles immediately after a SYNC event). DCLKoutX_DDLY_CNTH/CNTL, DCLKoutX_HS, and SDCLKoutY_DDLY can all be written at any time independently of SYSREF_CLR state.
...
1. Setting SYSREF_REQ_EN=1 links the SYNC pin to the SYSREF_MUX, overriding the current state and synchronously placing the SYSREF_MUX in state 0x3 (continuous mode). Setting SYNC_MODE=0 just ensures that the SYNC pin does not generate SYNC events or trigger the SYSREF pulser while this happens, so SYNC_MODE=0 is correct.
2. The pulser does not need to be powered on. SYSREF_MUX should swap to continuous mode from any state, including 0x2 (pulser mode) - even when the SYSREF pulser is powered down. So you should be able to power down the pulser and leave SYSREF_MUX in any state other than 0x3.
You can enable the feedback mux and route CLKout6 to OSCout - FB_MUX_EN should be set to 1, and OSCout_MUX should be set to the feedback mux output. As long as PLL2_NCLK_MUX selects the N-prescaler feedback, the PLL will continue to operate normally (single-loop, no zero-delay).
The global SYSREF digital delay is SYSREF_DDLY; the local SYSREF digital delay is SDCLKoutY_DDLY. In many cases, global SYSREF_DDLY can be set to the smallest value (8) without issue, and all device clock to SYSREF alignment can be performed using the local SDCLKoutY_DDLY. Occasionally there are cases where a device clock is particularly low frequency, such as with LMK04821 (same part with an extra ÷8 prescaler on VCO1) at 12.288MHz... in this case, to align the SYSREF to the device clock falling edge, a larger global SYSREF_DDLY is required. Otherwise, the largest available span depends on all other device clock digital delay settings, and global SYSREF_DDLY should be set such that SDCLKoutY_DDLY = 0x1 (2 cycles) corresponds to the 'bottom' of the adjustment range - I believe this is the same as your "smallest possible value."

Quick note, the latest revision of the datasheet (May 2020, SNAS605AS) has a typo in 9.3.4, equation 2 DCLKoutX_MUX_ADJUST should read:
DCLKoutX_MUX_ADJUST = 1 IF (Duty Cycle Correction DISABLED) ELSE 0
See datasheet section 10.2 for a detailed description of the PLL2_WND_SIZE and PLL2_DLD_CNT settings. Effectively, larger PLL2_DLD_CNT leads to higher PPM lock detect accuracy, but takes longer (more phase detector clock cycles) to measure.
...
1. A good example is when the divide is odd. Divide-by-27 cannot be achieved unless PLL2 prescaler is set to 3; divide-by-25 cannot be achieved unless PLL2 prescaler is set to 5.
2. Powering down the prescaler disables the prescaler output, and is not a bypass option. The prescaler cannot be powered down if the prescaler feedback path is used for PLL2. The prescaler powerdown only makes sense to use in zero-delay mode after the VCO is calibrated. This would look like:
  1. Follow programming sequence of 9.5.1, setting PLL2_PRE_PD=0 and PLL2_N_CAL such that the PLL can lock using the prescaler path.
  2. When the PLL N-divider is written, the VCO calibrates (to remove temperature effects) substituting the value of PLL2_N_CAL and using the prescaler feedback path.
  3. After calibration, the PLL2_NCLK_MUX is switched back to the feedback mux path, and the N-divider is returned to the programmed value in PLL2_N.
  4. As long as the VCO does not need to be recalibrated (no change in frequency, no excursion outside of allowable temperature range), PLL2_PRE_PD can be set to 1 to achieve extra power savings.
Normally, CPout1 is driven by a phase detector and charge pump. In holdover, the output of the phase detector is invalid, so the charge pump is tri-stated and the CPout1 voltage is instead set by a 10-bit DAC. That way, even if the clock inputs are lost for some reason, the DAC can set an output voltage to control the tuning pin of the PLL1 VCXO, preventing the VCXO from crashing into one of the rails and pulling PLL2 off-frequency. There is also a rudimentary sample-and-compare loop that can track the CPout1 voltage to automatically update the DAC value to the closest step value while PLL1 is locked. The user could manually set the DAC value based on known values for the VCXO at that temperature or based on some external PPM compensation/timestamping scheme; or, they could set TRACK_EN=1 and the DAC value will closely approximate the actual CPout1 value sampled just before switching to holdover.

Regards,

0 Beni Falk over 5 years ago in reply to Derek Payne

Prodigy 110 points

Derek,

Thank you very much for the extremely quick and detailed answer. Your support is outstanding.

Regards,

Beni Falk

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LMK04828: device configuration-related questions