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LMK04828: PLL1 unlocked in zero delay mode

John Polak
Prodigy 151 points
Part Number: LMK04828

I am using the LMK04828 with a 5MHz reference to generate 100MHz from PLL1, then using PLL2 to generate 325MHz. I have gotten a design working in cascaded mode (PLL1 feedback from OSCin).

My problem is that when I attempt to set the LMK04828 to zero delay mode (PLL1 feedback from DCLK6 or DCLK8) PLL1 never locks. PLL2 is locked in both cases. In both cases CPout1 is appox 1.65V, does this suggest a false loss of lock report?

The only change to the working design was to set PLL1_NCLK_MUX to take input from FB_MUX and change the PLL1_N from 10 to 65. I have confirmed that I have the FB_MUX_EN bit set high in both cases.

What could be causing this problem?

  • 0
    TI__Mastermind 33560 points

    Hello John,

    Just to confirm, is DCLK6 or DCLK8 enabled and dividing to the desired frequency? For example, if DCLK6 is set as the feedback to PLL1, you must set CLKout6_7_PD=0 (the output format can be powerdown if DCLK6 is unused). It sounds like you are doing everything correctly, though I would expect PLL1_N to start at 20 for 100MHz VCXO (perhaps you are using the OSCin doubler for PLL2).

    Are you using the SYSREF signal? Is it possible that DCLK6 or DCLK8 are being reset by the SYSREF divider due to SYNC_DIS6 or SYNC_DIS8 bits set to 0?

    You can use the STATUS_LD1 and STATUS_LD2 pins to output a copy of the PLL1 R-divider and N-divider signals for manual debugging. This is useful for detecting certain issues (e.g. there is no N-divider feedback, the R-divider signal is intermittent, DCLK6 signal shows periodic interruptions due to SYSREF divider resetting output clock).

    Regards,

  • 0 in reply to Derek Payne
    Prodigy 151 points

    Hello Derek,

    Thank you for your time. You are quite right, PLL1_N should be 20 in cascaded mode (a silly math error on my part). Not sure why the LMK reports lock in that configuration. I tested the IC with PLL1_N = 20 and it did not lock.

    I found the real problem is in board layout. I did not place the 100 Ohm termination resistor close enough to the LMK04828. I removed the one that was much closer to the previous IC and placed 100 Ohm resistor between the pads of the decoupling caps close to the LMK04828. PLL1 is now locking for me as expected.