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LMK04828BEVM: TICSPRO software configuration

Aleena Jose
Prodigy 80 points
Part Number: LMK04828BEVM

Hi,

I have been trying to configure TICSPRO software for my application.
It requires 100MHz input frequency(Osc_in) and should produce 14, 80MHz output clock which is phase synchronized with input reference clock.
Is there any TICSPRO configuration settings or programming sequence that has to be followed.

Thanks

  • 0
    TI__Mastermind 18070 points

    Hi,

    My coworker will get back to you by the next business day.

    Regards,
    Hao

  • 0
    TI__Mastermind 33790 points

    Hi Aleena,

    I recommend setting `Single Loop 0-Delay` on the `Set Modes` page. Clicking this button will configure PLL1 powered down, and sets CLKout6 or CLKout8 as the N-divider feedback source through the feedback mux. VCO=2400MHz can achieve 100MHz phase detector and 80MHz output. The SDCLKout outputs can be configured to output the same output frequency as the DCLKout outputs by setting SDCLKoutY_MUX to `Device Clock` (0x0). With all DCLK dividers set to 30 and the digital and analog delays set to the same settings or disabled, if you synchronize all the DCLK dividers the zero-delay loop should pull them into a predictable phase alignment with the 100MHz input clock.

    For demonstration, I recommend toggling the `RESET` control in the `User Controls` page (0→1→0), then CTRL+L to write all registers (or you can click the equivalent toolbar function). You can also export the register settings as hex data from the `File` menu, and the data will be saved in the recommended register programming order.

    Regards,

  • 0 in reply to Derek Payne
    Prodigy 80 points

    Hi,

    Thank you for your response.

    I tried the above mentioned configurations in TICSPRO sw.

    I have set OSCin as 100 MHz and mode as single loop 0-Delay and have disabled all digital and analog delays, have set clock divider as 30.

    But I'm getting the VCO/Clock Dist Frequency as 3000 MHz and all the clock out as 100 MHz. Instead I need all the clock out as 80 MHz.

    Is there any setting I'm missing.

    Thanks.

  • 0 in reply to Aleena Jose
    TI__Mastermind 33790 points

    Hi Aleena,

    I apologize, I forgot to clarify an important piece of the instructions: Set the SYSREF divider to 100MHz (divide by 24), set SYSREF_PD = 0, and set the FB_MUX on the PLLs page to use the SYSREF divider. Set the N-divider to 1. Then, with VCO_MUX set to VCO0, set the VCO frequency to 2400MHz. Also, to make sure the VCO calibration algorithm runs properly, set PLL2_P = 2 and PLL2_N_CAL = 12. Now setting all the output dividers to 30 should yield the desired 80MHz outputs.

    The advantage of using the SYSREF divider as the feedback path to PLL2 is that you can also configure the SYSREF_MUX to reclock the SYNC event to the rising edge of the SYSREF divider output, which is necessarily in-phase with the OSCin input. That way, the synchronization procedure is trivial:

    1. Set all the digital delays on the device clocks as needed (this may take some manual tuning) and ensure the DDLY_PD is set to 0 for each clock
    2. Set the SYNC_DISx = 0 for all the output channels
    3. Set SYNC_MODE = 1 (pin), SYSREF_MUX = 1 (reclocked SYNC)
    4. Toggle SYNC_POL 0→1→0
    5. Set the SYNC_DISx = 1 for all the output channels to prevent unexpected SYNC events

    Regards,