• State
  • Locked Locked
  • Replies 8 replies
  • Subscribers 22 subscribers
  • Views 733 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK04826: clock not detected by fpga

prahlad govind
Prodigy 50 points
Part Number: LMK04826

I have programmed my lmk to give an LVDS output of 156.25 MHz ,which i am giving to my Mgt bank in virtex 7 fpga.

I then used this clock for Aurora ip-core and Ethernet sub-system ip-core, but both ip core shows that there is no pll-lock. Just for testing purpose I then put a crystal oscillator of 156.25 MHz as a input clock to fpga during which time both ip-cores are showing pll-lock. i need to make both ip-core working with the lmk but unable to make it work. I have attached screenshot of both the clock

 

OSC CLOCK P

Below fig shows is the clk output i am getting from one of LVDS line of lmk. .

Below fig shows is the clk output i am getting from one of LVDS line of lmk.

LMK   CLOCK P

Kindly Suggest.

  • 0
    TI__Mastermind 33690 points

    Hello Prahlad,

    Nothing about the clock input looks obviously wrong (although from the signal distortion, I'm not sure the clock N is being terminated properly in this measurement). We need more information.

    • Can you provide a schematic showing how the LMK04826 output is connected to the Virtex 7 FPGA?
    • Can you provide the register or TICS Pro programming file for the LMK04826?
    • Have you confirmed the LMK04826 is locked to its reference source?

    Regards,

  • 0 in reply to Derek Payne
    Prodigy 50 points

    Hello Derek,

    I have two different boards with the same problem.

    In Board - 1, I have temporarily connected oscillator output to FPGA to verify the code and it is working.
    In Board - 2, I am taking LMK output to FPGA but PLL is not locking.

    First Schematic 

    I am using oscillator clock for the below schematic on temporary basis to prove the code and it is working.

    To use the crystal oscillator output to FPGA, we have for now removed the highlighted capacitor & resistor and i have connected the oscillator output to FPGA_MGT_CLK_P and FPGA_MGT_CLK_N.

    Output of crystal oscillator goes through LVDS fanout buffer and then to the MGT bank of FPGA. Here by using the oscillator clock, I am not having any issue with the code.

    Second Schematic 

    I am using LMK clock for the below schematic. Here, LMK output is connected to MGT bank of the fpga through coupling capacitor.

    There are two clocks going to the same MGT bank. Tried both of them but still the issue remains same.

    Highlighted the output clocks that are used for Aurora & Ethernet IP Core(DCLK8 & DCLK10)

    * TICS Pro programming file for the LMK04826 *

    Below is the programming file for LMK04826 used for second schematic

    Fullscreen LMK1_LOW_SPEED.txt Download 
    R0 (INIT)	0x000090
R0	0x000010
R2	0x000200
R3	0x000306
R4	0x0004D0
R5	0x00055B
R6	0x000600
R12	0x000C51
R13	0x000D04
R256	0x010008
R257	0x010155
R258	0x010255
R259	0x010301
R260	0x010422
R261	0x010500
R262	0x0106F0
R263	0x010755
R264	0x010808
R265	0x010955
R266	0x010A55
R267	0x010B01
R268	0x010C22
R269	0x010D00
R270	0x010EF0
R271	0x010F55
R272	0x011008
R273	0x011155
R274	0x011255
R275	0x011301
R276	0x011422
R277	0x011500
R278	0x0116F0
R279	0x011755
R280	0x011810
R281	0x011955
R282	0x011A55
R283	0x011B01
R284	0x011C22
R285	0x011D00
R286	0x011EF0
R287	0x011F11
R288	0x012010
R289	0x012155
R290	0x012255
R291	0x012301
R292	0x012422
R293	0x012500
R294	0x0126F0
R295	0x012711
R296	0x012810
R297	0x012955
R298	0x012A55
R299	0x012B01
R300	0x012C22
R301	0x012D00
R302	0x012EF0
R303	0x012F11
R304	0x013019
R305	0x013155
R306	0x013255
R307	0x013301
R308	0x013402
R309	0x013500
R310	0x0136F1
R311	0x013701
R312	0x013820
R313	0x013903
R314	0x013A02
R315	0x013B00
R316	0x013C00
R317	0x013D08
R318	0x013E03
R319	0x013F00
R320	0x01408B
R321	0x014100
R322	0x014200
R323	0x014311
R324	0x0144FF
R325	0x01457F
R326	0x014618
R327	0x01471A
R328	0x014802
R329	0x014942
R330	0x014A02
R331	0x014B16
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015003
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x015478
R341	0x015500
R342	0x015678
R343	0x015700
R344	0x015896
R345	0x015900
R346	0x015A78
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E00
R351	0x015F0B
R352	0x016000
R353	0x016101
R354	0x0162A4
R355	0x016300
R356	0x016400
R357	0x01650A
R369	0x0171AA
R370	0x017202
R380	0x017C18
R381	0x017D77
R358	0x016600
R359	0x016700
R360	0x016805
R361	0x016959
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E13
R371	0x017300
R8189	0x1FFD00
R8190	0x1FFE00
R8191	0x1FFF53

    * Confirmed the LMK04826 is locked to its reference source *

    yes we have seen that pll2 is locked by checking ld2 status of LMK.

    Please look into the above given details and suggest us the better way to make Board - 2 work with LMK. Awaiting for your reply.

    Regards,

    Prahlad.G

  • 0 in reply to prahlad govind
    TI__Mastermind 33690 points

    Hello Prahlad,

    Thanks for sharing your schematics and register programming. Here's what I observe, in order of priority (first is highest priority):

    • Register programming shows OUT4/5 are configured as LVPECL, but schematic suggests LVDS. MGT_WFG_CLK_113 and MGT_WFG_REF_CLK_113 are likely not being delivered to their target.
    • PLL2_N_CAL register is set to 10, but PLL2_N is set to 5. PLL2_N_CAL should be set to the same value as PLL2_N to ensure the VCO calibration succeeds.
    • 100Ω termination on OSCin is on the wrong side of the input capacitors - should be located on source-side as per Figure 26 in the LMK04826 datasheet.

    Please make the necessary updates and let me know if the issue still persists.

    Regards,

  • 0 in reply to Derek Payne
    Prodigy 50 points

    Hello Derek ,

    Thanks for your recommendation 

    point 1,2

    Here is the new programming file with the recommendation 1 and 2 given by you but the issue still persists.

    Fullscreen 1104.HexRegisterValues.txt Download 
    R0 (INIT)	0x000090
R0	0x000010
R2	0x000200
R3	0x000306
R4	0x0004D0
R5	0x00055B
R6	0x000600
R12	0x000C51
R13	0x000D04
R256	0x010008
R257	0x010155
R258	0x010255
R259	0x010301
R260	0x010422
R261	0x010500
R262	0x0106F0
R263	0x010755
R264	0x010808
R265	0x010955
R266	0x010A55
R267	0x010B01
R268	0x010C22
R269	0x010D00
R270	0x010EF0
R271	0x010F55
R272	0x011010
R273	0x011155
R274	0x011255
R275	0x011301
R276	0x011422
R277	0x011500
R278	0x0116F0
R279	0x011711
R280	0x011810
R281	0x011955
R282	0x011A55
R283	0x011B01
R284	0x011C22
R285	0x011D00
R286	0x011EF0
R287	0x011F11
R288	0x012010
R289	0x012155
R290	0x012255
R291	0x012301
R292	0x012422
R293	0x012500
R294	0x0126F1
R295	0x012701
R296	0x012810
R297	0x012955
R298	0x012A55
R299	0x012B01
R300	0x012C22
R301	0x012D00
R302	0x012EF8
R303	0x012F00
R304	0x013019
R305	0x013155
R306	0x013255
R307	0x013301
R308	0x013402
R309	0x013500
R310	0x0136F9
R311	0x013700
R312	0x013820
R313	0x013903
R314	0x013A02
R315	0x013B00
R316	0x013C00
R317	0x013D08
R318	0x013E03
R319	0x013F00
R320	0x01408B
R321	0x014100
R322	0x014200
R323	0x014311
R324	0x0144FF
R325	0x01457F
R326	0x014618
R327	0x01471A
R328	0x014802
R329	0x014942
R330	0x014A02
R331	0x014B16
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015003
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x015478
R341	0x015500
R342	0x015678
R343	0x015700
R344	0x015896
R345	0x015900
R346	0x015A78
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E00
R351	0x015F0B
R352	0x016000
R353	0x016101
R354	0x0162A4
R355	0x016300
R356	0x016400
R357	0x016505
R369	0x0171AA
R370	0x017202
R380	0x017C18
R381	0x017D77
R358	0x016600
R359	0x016700
R360	0x016805
R361	0x016959
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E13
R371	0x017300
R8189	0x1FFD00
R8190	0x1FFE00
R8191	0x1FFF53

    point 3

    we are unable to change the 100Ω termination on OSCin as per Figure 26. please recommend an alternate for it.

    Regards,

    Prahlad.G

     

  • 0 in reply to prahlad govind
    TI__Guru** 107780 points

    Hi Prahlad,

    From what I can see:

    reference clock for PLL1 = 100MHz

    PLL1 phase detector frequency = 0.83333MHz

    VCXO frequency = 100MHz

    VCO frequency = 2500MHz

    PLL2 is locked.

    My question is, is PLL1 locked? I guess it is not. 

    The phase detector frequency of PLL1 is not ideal, please make it to 1MHz.

  • 0 in reply to Noel Fung
    Prodigy 50 points

    hello Noel,

    as you go through with the above discussion, we are not using PLL1.

    input is given to OScin of PLL2.

    regrads

    Prahlad.

  • 0 in reply to prahlad govind
    Prodigy 50 points

    Hello DEREK,

    i couldn't find any solution for my problem.could you please look into it.

    sorry, Last time as i have sent you the wrong configuration file. i have attached the new configuration in the above discussion. but dint hear from you there after

    could you please look into it.

    Regards

    Prahlad

  • 0 in reply to prahlad govind
    TI__Guru** 107780 points

    Hi Prahlad,

    OK, so you are not using PLL1, then you can remove PLL loop filter.

    You said PLL2 is locked. If it is locked, then the frequency will be correct. Could you use a spectrum analyzer to measure the output clock? I want to know if it is stable and the frequency is accurate. Please also use a scope to check the voltage at CPOUT2, it should be a stable voltage at around 1.25V. 

    Do a debug experiment to remove the 100Ω resistor that is connecting OSCin pins. What is the signal format on the left side of the DC-blocking capacitors? If it is LVDS, put the 100Ω resistor there to terminate LVDS driver properly.