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LMH1983: Switching between 148.5 MHz and 148.35 MHz

Darren Jenkins
Genius 12461 points
Part Number: LMH1983
Other Parts Discussed in Thread: LMH1297

Clocking team,

Our customer is using LMH1983 to provide clocks to an FPGA and LMH1297. They’re concerned about jitter, especially at 12G rates. They want to switch between 148.5 MHz and 148.35 MHz, and minimize jitter.

I believe the way to do this is to use PLL2 for 148.5 MHz and PLL3 for 148.35 MHz, then switch using the Crosspoint. Is there a better way to do this that minimizes jitter? Will disabling the unused PLL reduce jitter?

I don't think it's possible to configure PLL2 to provide 148.35 MHz.  Can you confirm if that's correct?

Thanks,
Darren

  • 0
    TI__Expert 6140 points

    Hi Darren, 

    That is correct, PLL2 can output 148.5 MHz and PLL3 148.35 MHz. I've copied the excerpt from the datasheet below. 

    Disabling the unused PLL will save power, which in turn will lower the devices junction temperature. So it should have some benefit in lowering jitter. 

    Thanks and regards,

    Amin 

    8.3.3 Control of PLL2 and PLL3

    PLL2 and PLL3 have the least amount of flexibility of the four PLLs in the LMH1983. They are pre-programmed to run at 148.5 MHz and 148.35 MHz respectively. There is a divide-by-two option available to allow the output to be 74.25 MHz or 74.18 MHz, should these frequencies be required. These two PLLs can also be disabled – disabling PLL2 or PLL3 can save significant amounts of power if that particular clock is not required. Figure 11 shows a simplified functional block diagram of PLL2 and PLL3.