• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 20 subscribers
  • Views 653 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMX2594: Is a Square Wave input signal at OSCin improving the spurs?

Franz Castro
Prodigy 50 points
Part Number: LMX2594
Other Parts Discussed in Thread: PLLATINUMSIM-SW

Hello together,

I was wondering, if the input signal at OSCin (PIN 8/9) is a square wave signal, might improve the spurs in the frequency domain in the region from 0 Hz -> f_Lo.
I did read in the data sheet (if I understood it correctly) that the slewrate of the input signal is directly related to quality of the frequency domain output.

Is this related to the integer devider?

Thank you for your time. :-)



  • 0
    TI__Mastermind 28011 points

    Franz,

    The faster slew rate is preferable as any noise riding no the signal has less impact.  Furthermore, this applies to any internal crosstalk on the chip as well.

    If the divider is bypassed, this is still true, so this leads me to believe that the impact is at the phase detector or input buffer.

    Differential input is best for spurs as I have seen.  Furthermore, I have heard recent claims that if you do drive differential, then increasing the AC coupling capacitor at the OSCinP/M pins (say from 0.1 uF to 1 uF) may improve spurs as well.

    Regards,

    Dean

  • 0 in reply to Dean Banerjee
    Prodigy 50 points

    Hi Dean,

    thank you for your fast reply. Unfortunately I couldn't confirm your answer.
    By changing the DC-Block capacitor nor by driving the device single ended nothing did change.

    The spectrum at LO-Out is absolutly the same. I mean the output is pretty good with 75 - 80 dBc. But I couldn't find out any reason why I shouldn't drive the LMX with a single ended 100MHz input.

    Greetings Franz :-)

  • 0 in reply to Franz Castro
    TI__Mastermind 28011 points

    Franz,

    Spurs are tricky as they are dependent on so many causes.  It's hard to say if -75 to -80 dBc is good or bad because there are so many factors that dramatically impact spurs.

    Have you tried to compare the spurs you are getting with our PLLatinum Sim tool (ti.com/tool/PLLATINUMSIM-SW)?

    These simulations are based on performance metrics that we get from measurements we get in our setup.  The spur simulations are not something I would totally take to the bank, but it at least gives something to compare against.

    Regards,
    Dean

  • 0 in reply to Dean Banerjee
    Prodigy 50 points

    Hello Dean,

    In my case only -65 dBc to the highest spur are sufficient so I'm fine with the result.
    I will try to figure out how to use the PLLatinum Sim Tool. Thanks for that advice.

    I think I'm fine with your answere at this point. Maybe also any register is set wrong.

    By the way - I really appreciate your book PLL Performance, Simulation and Design.
    Since I'm a fresh graduadet engineer it helps me to get a foot into PLL Design!

    Greetings Franz