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LMK05318B: lock time problem

Part Number: LMK05318B

Hello,

   A new application need to use PLL,  need quickly lock.  please help check LMK05318B set time and lock time. 

   for example, LMK05318B had set output clock 10MHz, In the process of application, need to set output clock 11MHz.   need to set registors again and waiting for PLL lock. how long the time? 

   thanks.

  • Hi Xinjian,

    We will get back to you in next week.

  • Hello Xinjian, 

    Is DPLL needed in this application or not? APLL (analog PLL) lock time is very different from DPLL (Digital PLL). 

    If intent is to just use as a clock gen and lock APLL to XO, lock time should be very fast. There are some registers that can be updated to slightly improve lock time, but usually there's no need to do this. 

    If DPLL is needed for the system (network synchronization, lock to a 0 ppm reference, DCO mode, etc.) then DPLL lock time is dependent on reference validation timer, DPLL lbw, and TDC rate. 

    Thanks and regards,

    Amin 

  • Hello Amin

       DPLL need in application.  which means, when set pll again, need DPLL and APLL lock again.  i just want to know the max lock time, consider the lbw and reference clock.   or  whether the lock time <1ms (DPLL and APLL set again and lock)

       thanks.

  • Hi Xinjian,

    The DPLL lock time can be found here (the new wizard for LMK05318B)

    APLL lock time is APLL wait time (<1ms for APLL1, 3ms for APLL2) + PLL analog lock time, which is approximately 1/BW (<1ms for both APLL1 and APLL2).

    Regards,
    Hao

  • Hi Xinjian,

    Also letting you know that reference validation also takes time:

    The details can be found in the instructions box in that new wizard.

    Regards,
    Hao