This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK04832: Holdover function

Part Number: LMK04832

I have an LMK04832 fed by a 10 MHz source through a balun into CLKIN0. The input buffer mode is set to bipolar, so I can't use the LOS detectors. For backup, I have an LVDS signal (also at 10 MHz) into CLKIN1, this has worse phase-noise than the main input. I can switch between CLKIN0/1 using the CLKinSEL_MANUAL bits in R 0x147.

I would like to use the holdover function so the part will force the VCXO to be stable in the event of a dropout. With R 0x150=37 (HOLDOVER_EN=1, exit mode DLD, PLL1_DET=1, VTUNE_DET=1, CLKin_SWITCH_CP_TRI=1), I see that when I switch from CLKin0 to CLKin1 (or vice versa), the device enters holdover for a few seconds, then regains lock. If I disconnect the CLKin0 cable, however, PLL1 goes unlocked, but HOLDOVER is never asserted. Why doesn't the device enter holdover even though PLL1 is out of lock in this case? I tried fiddling with the DAC trip values, but no luck.

Another question about holdover: When I allow my system to stabilize, the DAC value is normally about ~640 counts. On start up, the DAC is at 512 and takes some time to reach 640. If holdover is enabled during this time, DLD will not be asserted since there is no phase match between the ref clock and wherever the VCXO gets tuned, so the device will never leave holdover. When using bipolar inputs (and therefore no LOS signal), is there a reliable way to exit holdover when the DAC value is not close to it's 'normal' one?

Finally, is there a penalty to using MOS inputs in my case? I use Bipolar following the data sheet recommendation for differential inputs.

Thanks in advance.

  • 1, Select a switching mode as datasheet showed.

    8.3.6.1 Input Clock Switching - Manual Mode
    8.3.6.2 Input Clock Switching - Pin Select Mode
    8.3.6.3 Input Clock Switching - Automatic Mode

    2, For manual setting holdover, it is easy to use HOLDOVER_FORCE =1 in Reg 0x14B to enter holdover status.

    3, DAC ~640 means there is a few frequency offset for CLKin noninal10 MHz and VCXO nominal center frequency. It doesn't matter.

    In such case, you can set MAN_DAC at 640 if using MAN_DAC_EN.

    Readback DAC from 512to 640, it means PLL is locking.

    4,Auto-exit holdover have to rely on a close frequency offset between CLKin and holdover frequency, which is hard to control.

    So I suggest to use manually enter holdover (HOLDOVER_EN=1, HOLDOVER_FORCE =1, MAN_DAC_EN =1, MAN_DAC= a value from 512 to 640),

    manually exit holdover (HOLDOVER_FORCE =0), do not use other conditions to trigger holdover.

    5, MOS type limited max frequency up to 250 MHz, need a higher swing than Bipolar.

    For your 10 MHz input, just focus on VIL and VIH for CLKin CMOS type.

    6, If the problem had not been solve, please use TICS Pro to set register value, save them as .tcs file. TI can load the file and check all register setting.

  • lmk04832_config.tcs

    Hi Shawn,

    I've attached the TICS PRO file here, I used this config with a few modifications (like setting SYNC/SYSREF mode), but the holdover registers are the same as those in the .tcs file.

    Manual holdover works fine, I can force holdover on/off without issue. My problem remains though that the device doesn't reliably enter holdover when PLL1 goes out of lock, even though HOLDOVER_EN, HOLDOVER_PLL1_DET and HOLDOVER_VTUNE_DET are all set. Please let me know if I have something misconfigured that's preventing this.

    Thanks!

  • Observed  internal status on Status_LD1 or Status_LD2 pins by programming PLL1_LD_MUX or PLL2_LD_MUX,
    respectively. Especially for below blue definitions.

    Field Value MUX Value
    0 (0x00) Logic Low
    1 (0x01) PLL1 DLD
    2 (0x02) PLL2 DLD
    3 (0x03) PLL1 & PLL2 DLD
    4 (0x04) Holdover Status
    5 (0x05) DAC Locked
    6 (0x06) Reserved
    7 (0x07) SPI Readback
    8 (0x08) DAC Rail
    9 (0x09) DAC Low
    10 (0x0A) DAC High
    11 (0x0B) PLL1_N
    12 (0x0C) PLL1_N/2
    13 (0x0D) PLL2_N
    14 (0x0E) PLL2_N/2
    15 (0x0F) PLL1_R
    16 (0x10) PLL1_R/2
    17 (0x11) PLL2_R(1)
    18 (0x12) PLL2_R/2(1)