Hello,
My design uses LMK04832 in a dual loop configuration. I use CLKIN2 for 10MHz LVDS reference for PLL1. In this setup, PLL1 does not lock.
I have tried to repeat this setup on the LMK04832EVM, but PLL1 would lock only on clock inputs 0 and 1, but not on CLKIN2 (it is enabled, either MOS/Bipolar, output is in powerdown).
is there a special register sequence that will enable the use of this input?
I have repeated the test on LMK04828EVB, but got the same results.
also, when I try to see PLL1_R, PLL1_R/2, PLL1_R/4 on both components, I see something that looks like an output of a phase detector and not a divided reference.
Thanks
Itamar