• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 22 subscribers
  • Views 744 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

LMX2572: Lock time is much longer than excepted

LMX2572: recommended register programming order for fastest locktime using double buffering and fiull assist

Brian Koenigsmark
Prodigy 40 points
Part Number: LMX2572

Support/Dean,

I am using the LMX2572 (for power reasons) and I am trying to achieve the fastest locktime possible over the full VCO octave range and CHDIV range from (2-4).  My frequency range/frac mode/reference frequency will require PFD_DLY_SEL to change. In addition I will implementing spur avoidance using PLL_R and MULT. Full assist is implemented and this is my programming order.  It is divided into pre-frequency change and post freq change. 

My assumption is that I can save a small amount of time by using double buffering, I would send the non-double buffered values (cap.idac,vco) and then the FCAL_EN=1 (double buffer).  Is this the correct assumption and the double buffer works in conjunction with full assist?

This is just for frequency changing, all other fixed values are preloaded

Pre-Frequency change

MASH_ORDER (double buffered)

PLL_NUM_LSB (double buffered)

PLL_NUM_MSB (double buffered)

PLL_N_LSB (double buffered)

PLL_N_MSB (double buffered)

PLL_R  (double buffered)

PLL_R_PRE  (double buffered)

MULT  (double buffered)

Post-Frequency Change

VCO_SEL (1st toallow the vco to settle)

VCO_CAPCTRL (2nd for cap settle)

FCAL_EN=1 (3rd load all double buffer regs to start freq tuning)

VCO_IDACCTRL (4th because less critical to locktime)

PFD_DLY_SEL (5th because less critical to locktime)

CHDIV (6th not critical top locktime, but would this cause glitch in locking while switching)

While this is similar to the previous email it does ask a couple questions.  

  1. Is my order correct for fastest settle?
  2. No issues with double buffering in full assist?
  3. does chdiv changing effect VCO acquisition?
  4. Any issue with slower locktime due to changing PLL_R/MULT?  
  5. Should spur avoidance be avoided if fastest locktime is required even though they are double buffered?

Thanks for any feedback, any detail of previous experience help due to the extremely fast lock times and the difficulty debugging.

Brian

  • 0
    Prodigy 40 points

    One additional issue, since spur avoidance is being used, this means CPG would be required to optimize the locktime when modifying the phase detector frequency.  Since this isn't double buffered i assume the best place for this register is before the FCAL=1 but after VCO_CAPCTRL

  • 0 in reply to Brian Koenigsmark
    TI__Guru** 107830 points

    Hi Brian,

    The new values for the registers with double buffer enabled will not be effective until FCAL_EN=1 is loaded. But when FCAL_EN=1 is loaded, calibration will take place. If I remember right, full-assist and calibration cannot coexist. I can check this out in next week.

    if you have a bunch of register to write, you have to write them fast. A register write will take 1µs when SPI CLK is 25MHz. 

    CHDIV is outside the PLL loop, it will not affect lock time.

  • 0 in reply to Noel Fung
    Prodigy 40 points

    Noel,

     

    The issue with double buffering and full calibration being not compatible was my concern. 

     

    The reason I think it might work, is because when setting up full assist you select the force registers which will bypass calibration.  I understand that double buffering will not completely work because the cap and idac still need to be programmed before the fcal happens. 

     

    The reason I provided the full list of my programming requirements is when you combine spur reduction registers along with NOT double buffering then you end up with 14 registers. At 24MHz (my clock) this is 14usec.  That is a very large percentage of the analog locktime.  By using double buffering I can reduce the programming time by 8usec which is a much lower percentage of the total lock time

     

    Please keep me informed to the results of your test.  Coding this up takes significant time and I don’t want to arrange my code for double buffering if it will not work

     

    Brian

     

  • 0 in reply to Brian Koenigsmark
    TI__Guru** 107830 points

    Hi Brian,

    I should have test result in this week, we have restriction to go to the lab due to COVID. Stay tuned.

  • 0 in reply to Noel Fung
    TI__Guru** 107830 points

    Hi Brian,

    I am able to check this over a remote bench, double buffer works in full-assist mode. You can first of all, program all the double buffered registers, then program the three VCO parameters, followed by R0 to make the buffered registers effective. 

    The remote bench setup does not support transient measurement, I cannot verify the impact of programming R0 to the switching time.