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Original question:

LMK04803: Calculating device power/current consumption

LMK04803: Power consumtion

user5884477
Prodigy 110 points
Part Number: LMK04803
Other Parts Discussed in Thread: CDCUN1208LP

Hi,

My design requires 14 outputs LVCMOS with minimal jitter.

All outputs are at 40MHz and must be synchronized. Input is also 40MHz but can be changed.

I calculated 865mW + 613mW (1478mW) of power dissipation. See pictures below.

Is there a way to reduce power consumption? Are the calculations correct?

Is there another device that could do what I need with total power around 500mW or less?

Thanks

  • 0
    TI__Guru** 110880 points

    Hi There,

    If you use it as a buffer only, will you consider to use a real fanout buffer like CDCUN1208LP?

    I will have our buffer people look into possible solution, stay tuned.

  • 0 in reply to Noel Fung
    Prodigy 110 points

    Hi,

    2:8 buffer is not enough. I need at least 1:14 (or 2:14, 1:16 ...).

    I need all output to be on the same chip to get good timings and low jitter.

    Maybe if I use 2 buffers and use both SYNC to synchronize all 14 outputs it could work, but this sounds problematic for my application. I prefer to use a single chip for all 14 outputs.

    This new buffer is needed to replace 87016AYILF and 8343AY-01LFT.

    Thanks

  • 0 in reply to user5884477
    TI__Guru** 110880 points

    Hi There,

    the 8 diff buffers can be configured as 16 CMOS buffers.

  • 0 in reply to Noel Fung
    Prodigy 110 points

    Hi,

    Just to make sure, all 16 LVCMOS output of CDCUN1208LP are synchronized?

    In other words, all rising edges are at the same time?

    Also, is the CDCUN1208LP going to work just fine with this configuration? : 

    Input: LVCMOS 1.8V

    VDD = 1.8V

    Output: LVCMOS 3.3V

    VDDOx = 3.3V

    Thank you

  • 0 in reply to user5884477
    TI__Intellectual 770 points

    Hi,

         Based on the datasheet specification, it should not be a problem with the configuration you have provided:

    Input: LVCMOS 1.8V

    VDD = 1.8V

    Output: LVCMOS 3.3V

    VDDOx = 3.3V

    I would like you to know that the outputs will be synchronized for all practical purposes and what you need to look for is the channel to channel skew in the datasheet. The max skew in the LVCMOS mode is 90 ps is 3.3 V assuming all outputs are loaded equally. This means that you can see a maximum of 90 ps difference between the rising edges of any outputs.