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Original question:

CDCP1803: 1 to 3 Fan-out Buffer solution

CDCP1803: Termination resistor is needed

abhishek Kumar
Prodigy 90 points
Part Number: CDCP1803


Hi TI Team, 

I am using the 1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER Part No- CDCP1803RGET in my project.

I have some doubt , Please see the below one and kindly reply.

Question1-It is recommended in the datasheet , we need to connect the termination resistor 100Ohm at the differential input (IN+, IN-).

                  Please refer the below screen cut attachments.(Ref Datasheet- Pg-13)

                  Is this we have to follow the same if I am getting the LVDS differential input from 10MHz clock generator (Part No- Si570)?

Question2- For the selection of the Select line(S0,S1,S2) , I am following the datasheet page-5 Table-1.

But i have some doubt for value of selectlie that is assigned for the S0, S1, S2( ex- in the table some time the value for S0 is 0 & 1 -> OK But VDD/2 ?-> Signifies ?

We have 3 selectline then why we are making the table for 32 Output states ?Please elaborate the Table1.


Question 3- The max sgnaling Rate Up to 800-MHz. But i have found one application report for the same part No. They are showing the eyediagram up to 1.5Gbps.

please the application report. Kindly suggest me how they are using for this IC for Gbps.(Application Report SCAA074–September 2004)

CDCP1803RGET_Eye diagram.pdf

 

  • 0
    TI__Genius 16845 points

    A1. For an LVPECL input, you do not need to use the 150ohm bias resistors. 

    A2. For VDD/2, this is halfway between 0 and 1 (GND and VCC). This allows more options than purely binary

    A3. 800MHz max frequency in the datasheet is the maximum frequency at which datasheet performance is guaranteed. As shown in the app note, performance outside of this range is still possible, but not specified.

    Kind regards,
    Lane

  • 0 in reply to Lane Boyd
    Prodigy 90 points

    Hi TI Team, 

    Thanks for your reply!.

    It helps me for my project.

    I have one another doubt-> The Part No- CDCP1803RGET, I am getting the 3 differential clock output for the different radio application.

    Any termination resister is needed at the output ie we can VBB Bias will be with range 2V to 1.8V.

    Any attenuation is needed here ?

    Please confirm me.

    Thanks 

  • 0 in reply to abhishek Kumar
    TI__Mastermind 28560 points

    Hello Abhishek,

    One quick note on your prior question #3, the app note is within specification.  1500 bits per second is equivalent to 750 MHz clock.  Consider a data stream consisting of alternating 1s and 0s.  Then you have a clock.  If AC coupling, you need to make sure your data is DC balanced.

    As for your question on the output, I'm not sure the input requirements of your receiver.  Please take a look at application note SCAA059.  ()

    However you wouldn't generally bias the output to Vbb.  In general for an LVPECL output you must have a DC path to Vcc - 2 V or ground.  50 ohms to Vcc - 2 V (Vbb) is the simple thing for DC coupled LVPECL if Vbb is offered.  When not dealing with LVPECL receivers, often the simplest thing to do for LVPECL is to operate AC coupled.  To do so, place 120 ohm to 240 ohm resistors on each output pin to ground.  These are called emitter resistors and would be placed close to the LVPECL output.  Higher resistance values can be used like 240 ohms to reduce current consumption but will also slow down edge rates.  Then in series with each output pin is a DC blocking capacitor, often 0.1 uF is a good value.  These capacitors could be placed close to the transmitter or receiver.  Then at the receiver, place a 100 ohm termination across the input if it is not integrated.  This is similar to Figure 6 in the app note above.

      - Ideally the receiver will self bias, if not you do need to provide a circuit similar to figure 5 to bias appropriately.  Check your receiver datasheet.

    If you want to do DC coupled LVPECL, again nothing is required at the output.
      - If your receiver provides a Vbb, you can simply place two 50 ohm resistors on each P and N line to Vbb.
      - If your receiver does not provide Vbb, you can use a circuit as shown in Figure 10 of the CDCM1803 datasheet.
      - Finally on additional option for DC coupling LVPECL is a Y-termination as illustrated below.  The voltage divider between the 50 ohm resistors create a nominal 50 ohms to Vcc - 2 V.

    73,
    Timothy