LMK04826: Request the TICS Files.

Hello Louis,

Please note that TICS Pro is designed as a customer self-serve tool, and we encourage the customer to try designing their profile first before requesting a profile from TI.

I have made some assumptions where the specifics were not provided:

• Device Clock/SYSREF is only aligned for 491.52MHz on device 1. The SYSREF leads the 491.52MHz clock by 180° of 491.52MHz signal, to allow device 2-5 to reclock SYSREF to the 491.52MHz clock distribution frequency for proper alignment on downstream devices.
• Device 1 uses pulser mode with SPI SYSREF generation, single pulse.
• Devices 2-5 use SYSREF with 2-cycle delay to put SYSREF on the falling edge of 122.88MHz. For 491.52MHz, SYSREF is aligned with 3.5 cycle delay to ensure the concurrent 122.88MHz/491.52MHz edge is used to latch the SYSREF event.
• All devices use digital delay and will need to be synchronized to ensure proper alignment of outputs. No device's SYNC is timing critical, so the SYNC signal can be delivered by software - set SYNC_MODE=0x1, SYSREF_MUX=0x0, and toggle SYNC_POL in SPI to trigger a SYNC event.

Regards,#936316 E2E.zip