Other Parts Discussed in Thread: LMK03328
Dear colleague,
Our customer has a concern about LMH1983 phase noise.
They viewed the below post:
https://e2e.ti.com/support/interface/f/138/t/744331?tisearch=e2e-sitesearch&keymatch=12G%252520SDI
These two posts mentioned that the phase noise of the 148.5M and 148.35M clocks output by LMH1983 cannot meet the requirements of XILINX Kintex ultrascale FPGA.
If the 148.5M and 148.35M clocks output by LMH1983 are directly used as the reference clock input of Kintex ultrascale SERDES, the jitter of the 12G SDI signal output by the FPGA may not reach the SMPTE standard. Their current design is also like this, and the jitter of the tested 12G SDI signal does exceed the standard (Alignment jitter is around 0.5UI).
The post also mentioned that LMK03328 or other low-noise phase-locked loop chips can be used to connect the 27M clock input of LMH1983, and the low jitter 148.5M and 148.35M clock output by LMK03328 can replace the 148.5M and 148.35M clock output by LMH1983 as the reference for FPGA clock input.
So,
1. For the design of 12G SDI, is the jitter of the 148.5M and 148.35M clock output by LMH1983 sufficient?
2. Does they need to add a low-noise phase-locked loop chip (such as LMK03328) to meet the SMPTE standard?
Best Regards,
Rock
