Hello all,
CDCI6214is using to generate clk1 and clk2 to driving two 14bit, 100M, ADC.
I am thinking if CDCI6214could generate two 180 phase delayed clocks, i.e. driving two 100M ADC in reversed-phase?
Or is there any other solution, such as cascade another bypass-able phase invert IC?
Thanks, any input will be appreciated.
there is a ' 5bit digital delay ' in CDCI6214, but I am not sure what's the function exactly.
Hi Hai,
Yes this can be done through the digital delay functionality.
For example, the VCO frequency is 2400MHz and the prescaler is 6. Output divider is 4. Output frequency is 2400 / 6 / 4 = 100MHz. There're 4 possible phases at the output, and what chx_sync_delay does is that it provides a phase delay after phase sync. The delay step size is one period of prescaler clock, which in this case is 2400/6 = 400MHz. In other words, to have 180-deg phase delay at the output, you can set chx_sync_delay = 2 for one channel, and = 0 for the other.
One more thing - CDCE6214 is more recommended. It is pin compatible with CDCI6214, but CDCE6214 is a newer device and we've made some improvements.
Regards,
Hao
