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LMK04828: locking problem

Part Number: LMK04828

Hi All

I am using the LMK04828 design based on the LMK04828EVM board.

i want to use the LMK to DRIVE 7 1 GHz outputs. I am using CLKin2 for input from SItimes 5510A TCXO (SE), and I use 122.88Mhz CrysTek 603281 VCXO (diff output) for the PLL1.

the LF values are in the scheme below.

when i program the LMK all the clock's output are fully functional, but the PLL's won't lock.

when i look on the scope on the CP1 or CP2 pins there is nothing there.

a interesting point is that if i put my finger on the board near the IC both of the PLL's locked immediately.

any ideas?

thank you

Shlomo Marmor

 

  • Hi Shlomo,

    Given that placing a finger on the board causes both PLLs to lock, this is likely related to the VCXO signal not getting to the OSCin port. My guess is LMK04828, the VCXO, or a component on the signal path from the VCXO to the OSCin port is not properly seated, and pressing on the board firms up the solder contact enough that the reference input sees a clean signal again. 

    Your image didn't load so I can't see the loop filter picture, can you repost if required?

    Regards,

  • hi thanks for your replay.

    i have checked, and i can see the 122.88Mhz on the OSCIN pins.

  • Hi Shlomo,

    Earlier you said there is "nothing there" on CP1 or CP2, does this refer to any noise or any voltage at all? What is the voltage on these pins while the device is unlocked, and while the device is locked with your finger on the board?

    I see your PLL2 loop filter R2 value is 12k. Should this be 1.2k? 12k generates significant peaking according to PLLatinum Sim.

    Regards,

  • Hi Shlomo,

    We haven't heard from you for a while, so I'm marking this thread as resolved. If you need additional support, please open a new E2E thread (and reference this thread, if relevant).

    Regards,