LMK04826: Multi Clock Synchronization

Hi Pavan,

Your constraints make it impossible to use a GCD frequency such as the SYSREF frequency to ensure all outputs are synchronized using the LMK04826, since the SYSREF outputs are not connected between devices and the device clock dividers are too small to generate 4.8828125MHz to force all outputs to be synchronized. The GCD of 100MHz and 4.8828125MHz is even lower at 195.3125kHz, which cannot be generated from a 2500MHz VCO even using the SYSREF divider, so there is effectively no way to guarantee input-to-output synchronization between the 100MHz signal and the rest of the system. If you could use the P2P-compatible LMK04832 instead of the LMK04826, you could get 2500MHz VCO and channel dividers large enough to generate 4.8828125MHz outputs from device clocks, or you could mux the SYSREF outputs to the device clock pins. But you stated that your hardware is fixed, so I assume switching to LMK04832 is not an option.

Are you able to synchronize the devices using an external SYNC signal on the SYNC pin? The SYSREF divider phase between devices will be different across power cycles due to differences in lock time, register programming time, ambient conditions, etc. If you can use the SYNC pin, you can ensure that every device receives a SYNC signal at roughly the same instant, reset the SYSREF dividers, and use a reasonable OSCin frequency such as 156.25MHz to satisfy the zero-delay requirements across the 156.25MHz/312.5MHz domains.

If you don't have anything connected to the SYNC pin, but you have device targets for your SYSREF that have test patterns, you can try reading back test pattern data from multiple devices simultaneously, quantify the error in terms of 2500MHz cycles, and use dynamic digital delay to shift the SYSREF of each device into the correct alignment. With this scheme, the zero-delay frequency could once again be something reasonable like 156.25MHz.

Each of the approaches above face challenges synchronizing to the 100MHz source. As long as you have something monitoring the 100MHz signal to keep track of the phase with respect to other LMK1 outputs, you could SYNC LMK1 and manually count 128 100MHz clock cycles for every 25 4.8828125MHz clock cycles. The whole system phase could be adjusted with respect to the 100MHz clock using dynamic digital delay, or by SYNCing to re-establish the digital delays.

Regards,

Hello Pavan,

pavan kumar8 said:

If I toggle the SYNC Poll bit through SPI configurations, then some of my clocks are drifted and synchronization is lost. Why??

Each time you send a SYNC signal to the dividers (whether through SYNC_POL bit or from an external signal), and while SYNC_DISx=0 for the divider in question, the divider is held in reset until the SYNC signal is cleared. Once the SYNC signal is cleared, each synchronized divider will begin counting some number of VCO cycles defined by the digital delay circuit. That said, in your configuration file I see that all the digital delay circuits are powered down. I'm not sure what your synchronization procedure is, so depending on the details (digital delays enabled, set to different values, SYNC_DISx=0, etc), your synchronization procedure could be changing phase relationships for a number of reasons. I need the SYNC procedure to offer a better response.

pavan kumar8 said:

I have provision to use Hardware SYNC pin. Is it required to use it ?? In the datasheet, it is given that SYNC_POLL toggling will give the same behavior as toggling the Hardware SYNC pin . Please clarify 

Toggling SYNC_POL would work to establish a phase relationship between clocks on the same device. But when multiple devices must be synchronized, the SYNC pin (or the CLKin0 SYNC source) is needed for timing precision, since the SPI clock is not necessarily synchronized to the VCO and the digital logic may have different response times over PVT.

In your use case, you have a choice: either you can use the SYNC pin to set the phase of the SYSREF divider on each device, or you can use some other procedure to compensate the SYSREF digital delay on each device so that the device-to-device SYSREF phase difference is always known between power cycles. Based on other information you provided in your post, it seems like determining the SYSREF divider phase may be less challenging than getting a consistent synchronization through the SYNC pin.

pavan kumar8 said:

If I use Zero delay mode with 156.25 MHz as feedback, then GCD( 2500, 312.5,156.25) = 156.25, so I can use 156.25 MHz as feedback clock and i will program OSCin of LMK2, LMK3, LMK4, LMK5 as 156.25 MHz, then all my device clocks will be synchronous and SYSREFs will not be synchronous across all the LMKs. Is it correct ??

This is correct.

pavan kumar8 said:

Is it required to Synchronize all the SYSREF pulses in JESD204b Protocol (Subclass 1) for Synchronizing multiple DACs ??

It isn't strictly required. However, you must be able to infer the number of cycles of difference between the SYSREF edge across multiple devices, and you would need to manually offset the buffers on your FPGA or your DAC to compensate. As I previously mentioned, the SYSREF divider phase will be random across power cycles between different devices, so each power cycle you would need some way to manually realign the SYSREF phases across devices.

pavan kumar8 said:

How can I send SYNC to all the 5 LMKs at the same instant ?? They are not length Matched 

If they aren't length-matched, you likely cannot send them at the same instant. You could set the digital delays to compensate for length matching differences on each device. For example, the longest SYNC path could use the smallest digital delay, and the shortest path could use longer digital delay.

pavan kumar8 said:

Are you referring to JESD Test Pattern ??

To be more specific, you would send something like a continuous ILA pattern, so that you can determine the appropriate elastic buffer for each DAC. The difficulty is in ensuring determinism between power cycles or system resets for whatever elastic buffer is established across all lanes. As long as the device-to-device SYSREF phase is the same between power cycles (either by using synchronization or digital delay adjustment), the elastic buffer setup will be the same between power cycles and determinism will be achieved. If the elastic buffer setup differs between power cycles, latency will be different at each power cycle. Technically it may be possible to work around this as well, but it comes down to how much compensation your JESD hardware can accommodate.

For more information, see the TI deterministic latency training.

pavan kumar8 said:

For all the above experiments do we need to continuously monitor phase of 100 MHz input to LMK 1 ??

Only if you care about the phase of the 100MHz clock related to the 156.25MHz/312.5MHz domain. Usually with JESD204B systems, any clock not in the JESD204B domains does not need to be synchronized, but this is application-dependent. You seemed to suggest it would be okay for only the outputs to be aligned across devices, so I suspect you do not need the 100MHz phase.

pavan kumar8 said:

What is the relation for 128 100MHz clock cycles to sysref ?

I was off by a factor of 4, it should be 512. GCD(100MHz, 4.8828125MHz) = 195.3125kHz; 100MHz/195.3125kHz = 512; 4.8828125MHz/195.3125kHz = 25. But based on the above, this may not be important since the 100MHz clock may not need to be aligned to the other clocks.

Regards,