8.3.4.2 Dynamic Digital Delay
For the SYSREF divider an alternate divide value will be substituted for the regular divide value.This substitution will occur a number of times equal to the value programmed into the DDLYd_STEP_CNT if DDLYd_SYSREF_EN = 1. To achieve one cycle delay as is done for the device clock dividers,set the SYSREF_DDLY value to one greater than SYSREF_DIV+SYSREF_DIV/2. For example,for a SYSREF divider of 100,to achieve 1 cycle delay, SYSREF_DIV= 100 + 50 + 1 = 151.
Does it mean that if I want to use Dynamic Digital Delay for the SYSREF divider, I should set the SYSREF_DDLY value?
I think that SYSREF_DDLY is Fixed Digital Delay.
8.3.5 SYSREF to Device Clock Alignment
Depending on the DCLKout_X path settings, local SCLK_X_Y_DDLY might need adjustment factor. Following
equation can be used to calculate the required Digital Delay Values to align SYSREF to the corresponding
DCLKout:
SYSREF_DDLY = DCLKX_Y_DDLY - 1 + DCLK_DIV_ADJUST + DCLK_HS_ADJUST - SCLK_X_Y_DDLY (1)
SYSREF_DDLY > 7; SCLK_X_Y_DDLY > 1.
Does "local SCLK_X_Y_DDLY might need adjustment factor" mean that the equation should start with "SCLK_X_Y_DDLY = "?
What does "SYSREF_DDLY > 7; SCLK_X_Y_DDLY > 1" stand for?
