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LMK04828: PLL1 locked sometimes while sometimes not?

Joseph Xu
Prodigy 170 points
Part Number: LMK04828

Hi support team,

I'm using FPGA to configure LMK04828. And I find sometimes LMK04828 PLL1 can be locked after power on. And sometimes I need to program it for a second time or third time to make it locked.

How should I do to make the LMK04828 PLL1 always locked after power on?

Thanks.

Joseph

  • 0
    TI__Mastermind 33430 points

    Hi Joseph,

    I have two possible explanations:

    1. While programming the device, the register value changes cause increased supply current, resulting in VCC drop-out and device reset. Sometimes this happens with inadequate supply pin bypassing on the digital pin, or with a high-impedance (>200Ω) ferrite bead on the supply net to the pin. You can confirm this by trying to read back the PLL1 settings that should have been written, and verifying that the results are as expected.
    2. Something about the register programming is causing the device to enter holdover, and the exit condition is never satisfied. I would need to see the register settings you are using to say for sure if this was the case, do you have a hex file or a tcs file if you are using TICS Pro to generate the configuration?

    If you could share your register configuration, that would be helpful in determining what is wrong.

    Regards,

  • 0 in reply to Derek Payne
    Prodigy 170 points

    Hi Derek,

    Thanks for your detailed explanations.

    Below are my LMK04828 setting file and snapshot, please help me.

    lmk04828_spi_rom_0delay_v6.tcs

  • 0 in reply to Joseph Xu
    TI__Mastermind 33430 points

    Hi Joseph,

    Just to be sure, you are trying to use an external VCO with PLL2? I will assume this is intentional based on the configuration.

    My first recommendation is to set CLKin_SEL_MODE = 0 to manually select CLKin0 for PLL1 reference input, since CLKin1 is used as Fin (3200MHz) and CLKin2 is used as OSCout. Having CLKin_SEL_MODE set to auto select may confuse the clock input selection state machine, and there is only one valid clock input anyway.

    Second, set PLL2_N_CAL = PLL2_N. At startup, PLL2 always starts with the PLL2_N_CAL divide value programmed to PLL2_N. This is used to calibrate the internal VCOs, but since you have selected 3200MHz external VCO for PLL2 the calibration is not necessary. However, on startup the PLL2 phase detector will see 1600MHz from the feedback path with PLL2_N_CAL = 1. Setting PLL2_N_CAL = PLL2_N will ensure that PLL2 always sees a consistent VCO feedback frequency.

    You could also disable the internal LDOs to save current by setting VCO_PD = 1 and VCO_LDO_PD = 1. Furthermore, I believe you can skip the VCO calibration switching N-divider values by setting PLL2_FCAL_DIS = 1 before programming the N divider. I believe setting PLL2_FCAL_DIS = 1 supercedes the need to set PLL2_N_CAL = PLL2_N, but there is no harm in setting PLL2_N_CAL = PLL2_N just to be safe as well. PLL2_FCAL_DIS is located on the User Controls page, under the PLL frame, in the PLL2 group.

    Regards,