Other Parts Discussed in Thread: LMK04208
Hi Team,
We've received a request from a customer for the configuration file to generate a clock out of multiple of 276.21Mhz. The LMK04208EVM has a 122.88 Mhz input osc in.
Regards,
Danilo
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Hi Team,
We've received a request from a customer for the configuration file to generate a clock out of multiple of 276.21Mhz. The LMK04208EVM has a 122.88 Mhz input osc in.
Regards,
Danilo
Hi Danilo,
LMK04208 is an integer N divider and an integer output divider. 276.21MHz does not share any common multiple with 122.88MHz within VCO range. They must change their OSCin frequency, or accept an extremely low PLL2 phase detector frequency which will degrade their phase noise performance. If they have an alternate VCXO frequency which they would prefer to use, which does share a common multiple with 276.21MHz within VCO range, I can suggest a configuration.
Regards,