LMK04828: In single-loop mode, PLL2 cannot lock

KGY

Part Number: LMK04828

Hi,

I am configuring the LMK04828 in single PLL mode as shown in figure12 below, to output DCLKs to 500MHz and 250MHz.

OSCin is 200MHz (LVDS). However, I cannot get PLL2 to lock. when I probed on OSCout, i can see a 200 MHZ output.

At DCLK, i can see output signals but the signals are at 491MHz and 246MHz. I have attached values that I program into the registers.

Is there anything that I have set wrongly?

Thanks.

Fullscreen lmk04828_single.txt Download

over 5 years ago

0 Aaron Black over 5 years ago

TI__Genius 16720 points

Hello,

I cannot see a figure in your request, this might have been broken in the attachment. Try and attaching this as you did with your '.txt' document.

The '.txt' file you have attached is not in a hex format. I would recommend exporting the hex register values as I can directly manipulate those values but your file seems to be missing addresses.

Please advise this additional information before I can help with looking at the issues of non-locking PLL2.

0 KGY over 5 years ago in reply to Aaron Black

Intellectual 310 points

Hi Aaron,

Thanks for your reply. I managed to get PLL2 to lock.

There is a mistake in the R divider value. After correcting it, PLL2 is locked.

Thanks.

0 Aaron Black over 5 years ago in reply to KGY

TI__Genius 16720 points

Hello,

That's great to hear you were able to solve your issue with PLL2 locking.

If further help is needed on this forum, please advise at that time. Otherwise, I will consider this request complete.

Clock & timing

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LMK04828: In single-loop mode, PLL2 cannot lock