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CDCE6214: Load capacitance clarification

Kristoffer Stenberg
Intellectual 1855 points
Part Number: CDCE6214

Hi CTS team,

I need some clarification on the application note; for load capacitance, the formula given is below; 

 CL =  CL1/2 + Cint_L1/2 + Cstray

CL is the load capacitance ; from the crystal spec, this is 18pF
CL1 is the external load capacitors – currently 10pF
CINT_L1 is the internal capacitance programmed in the device – form the settings this is 4.4pF
Cstray is approx.. to 3pF typically.


Using the formula ; 10/2 + 4.4/2 +3 = 10.2pF
 

Looking at the CINT_L1, which is programmed in IP_XO_CLOAD register;

  1. The description given is that the programmed value is the sum of the two internal load capacitors?
    Does mean that I don’t halve as suggested by the formula?
  1. It appears that this programmed value also allows for the CSTRAY capacitance 3pF, given that the value to ‘0 ‘ would still include the 3pF capacitance – described in the TICs GUI.


With Regards,
Kris

  • 0
    TI__Genius 11900 points

    Hello Kirstoffer,

    1. I believe you are correct, you do not have to divide the Cint set by IP_XO_CLOAD.
    2. Yes, setting IP_XO_CLOAD = 0, disables the internal load capacitors. The pin and package capacitance still add 3 pF, which would be encompassed as Cstray in the formula above. The IP_XO_CLOAD can then increase Cint_L1/2 in ~0.2 pF steps for each increment of the register value.

    Thanks,

    Vibhu

  • 0 in reply to Vibhu Vanjari
    TI__Mastermind 18070 points

    Hi Kristoffer,

    The description wasn't synchronized because at the time the appnote was published, the load cap in Ticspro was described in singled ended value. So you're right that the current Ticspro load cap is already halved, so no need to divide by 2 anymore. The 3pF is actually the internal load cap (circuit intrinsic + pin capacitance). It does not include the PCB stray capacitance.

    Regards,
    Hao