Hi,
I have a couple of questions that while the answer seems obvious there may be an advantage to configuring the synth in one manner vs another.
The application uses the LMX2594 with a 100MHz reference, 10 MHz Pfd frequency, No Assist and operates in INT mode.
After reviewing the DS and based on my knowledge of similar devices, I would set PLL_R_PRE = 1, MULT = 1, PLL_R = 10 and CAL_CLK_DIV would be set to divide by 4 in order to keep the Fsmclk less than or equal to the Pfd frequency.
Up until now however the registers have been configured such that PLL_R_PRE = 10 and CAL_CLK_DIV =1 with no apparent programming or lock problems even over the commercial operating temperature range which is a bit surprising to me.
I've been assuming that the minimum PFD frequency restriction outlined in Table 13 also applies when not using the ramping modes but perhaps my understanding is incorrect as this isn't explicitly stated on page 20, section 7.3.2.5 of the DS and page 46 states that setting CAL_CLK_DIV to 1 when operating with Fosc < 200MHz. is acceptable.
Do the minimum PFD restrictions outlined n Table 13 apply when not using ramping?
Is there any difference in the additive noise between the PLL_R_PRE and PLL_R dividers (or other reason) such that if the multiplier is not being used, one divider would be preferred over the other?
Thanks,
Marty
