CDCE937: Errors and conflicting information in datasheet of CDCE937 and family members: CDCE913, CDCE925, CDCE949

I am using CDCE937 for a new design. I want to use this part to generate 6 frequencies total, 2 frequencies per PLL using the associated dividers.
My questions are as follows:

1. Here are 2 examples of 'pairs' of frequencies (mhz).  Based on my calculations, I should be able to generate each pair using a single PLL and 2 "PDIV" dividers.

desired_freq    Actual_freq    N_parameter    M_parameter    R_parameter    Q_parameter    P_parameter    PDIV_parameter

1.561120    1.561151892    3072        483        213        25        2        110
1.807680    1.807649559    3072        483        213        25        2        95

1.602240        1.602268657    1491        335        269        17        2        75    
1.848800        1.848771527    1491        335        269        17        2        65   

The parameters listed are based on calculations of "Actual_freq" and "Actual_freq" is within 160 hz of "desired_freq" (which is acceptable)

Can you confirm that each pair can be generated using a single PLL ?

2. I am not familiar with using PLLs, can you explain why R = 0 is preferred ??

3. Can you state the true and correct limits on the parameters "P" and "R" ??

4. Can you fix the datasheet(s) for these parts?

I provide more details below.

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I have downloaded the part datasheet, here is the part number, web link, and revision information

CDCE937    www.ti.com/.../CDCE937    SLAS564G –AUGUST 2007–REVISED OCTOBER 2016

Also, I reviewed replies in the forum related to this family of parts. One particular thread
has replies by "Julian Hagedorn"
e2e.ti.com/.../332435

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Julian Hagedorn states:
    The PLL will be in fractional mode, if R is not equal to 0.
    The datasheet examples also suggest R = 0 is a good thing.

But the datasheet has inconsistencies on the limits on the parameters "P" and "R"
    Two pages within the datasheet give conflicting limits on these parameters.

1. I am not familiar with using PLLs, can you explain why R = 0 is preferred ??

2. Can you state the true and correct limits on the parameters "P" and "R" ??

Besides these inconsistencies there are typo errors in the equations on pages 25 & 26 of the datasheet.

Note: these types of errors are also present in the other "family member" datasheets
ex: CDCE913, CDCE925, CDCE949 and also the -Q1 parts

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There is an inconsistency between the limits placed on parameters "P" and "R"

Please refer to Page 25 and 26, under "9.2.2.2 PLL Frequency Planning"

Please also refer to Page 22, the footnote (5) between Table 11 and Table 12.

Page 25 and 26, list the limits as

N (1 to 4095)
16 ≤ Q ≤ 63
0 ≤ P ≤ 4
0 ≤ R ≤ 51

Page 22 lists the limits as

(5) PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096

Comparing the two pages, the limits for "Q" are consistent, and for "N" they are equivalent
However, the limits of "P" and "Q" are contradictory between the two pages.

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There is a typo in one of the equations:

Page 25 and 26, under "9.2.2.2 PLL Frequency Planning" show the equations and two examples
for calculating the output frequencies.

There is an error in the equation for P     P = 4 – int(log2N/M; if P < 0 then P = 0

There is a missing ")" to match "int("

If I were editing the text, I would add an extra pair of "( )" around N/M for clarification.

Note: this type of error is in the other "family member" datasheets, except CDCE925, which has a different typo.

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I could suggest incorporating some information written by "Julian Hagedorn" in this forum.

e2e.ti.com/.../332435

For example "In order to get the best performance N and M values should be maximized."