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LMK03328: Register configuration

Part Number: LMK03328


Dear colleague,

The following table is the register data exported after the customer configure the TICS PRO tool. Among them, R26, R48, R107-116, R121-130, R169, R172, and R173 are not specified in the data sheet and TICS PRO tool. How to deal with these registers when configuring LMK03328?

Thanks a lot!

Best Regards,

Rock Su

Register

R/W

Address

Setting data

Register function name

R0

R

0x00

0x10

VNDRID_BY1

R1

R

0x01

0x0B

VNDRID_BY0

R2

R

0x02

0x32

PRODID

R3

R

0x03

0x00

REVID

R4

R

0x04

0x00

PARTID[31:24]

R5

R

0x05

0x00

PARTID[23:16]

R6

R

0x06

0x00

PARTID[15:8]

R7

R

0x07

0x00

PARTID[7:0]

R8

R

0x08

0x00

PINMODE_SW

R9

R

0x09

0x00

PINMODE_HW

R10

R

0x0A

0x00

SLAVEADR

R11

R

0x0B

0x00

EEREV

R12

RW

0x0C

0xDF

DEV_CTL

R13

R

0x0D

0x00

INT_LIVE

R14

RW

0x0E

0x00

INT_MASK

R15

RW

0x0F

0x00

INT_FLAG_POL

R16

R

0x10

0x00

INT_FLAG

R17

RW

0x11

0x00

INTCTL

R18

R

0x12

0x00

OSCCTL2

R19

RW

0x13

0x00

STATCTL

R20

RW

0x14

0xFF

MUTELVL1

R21

RW

0x15

0xFF

MUTELVL2

R22

RW

0x16

0xFF

OUT_MUTE

R23

RW

0x17

0x02

STATUS_MUTE

R24

RW

0x18

0x00

DYN_DLY

R25

RW

0x19

0xF5

REFDETCTL

R26

?

0x1A

0x00

?

R27

RW

0x1B

0x58

STAT0_INT

R28

RW

0x1C

0x28

STAT1

R29

RW

0x1D

0x02

OSCCTL1

R30

RW

0x1E

0x1C

PWDN

R31

RW

0x1F

0x20

OUTCTL_0

R32

RW

0x20

0x20

OUTCTL_1

R33

RW

0x21

0x06

OUTDIV_0_1

R34

RW

0x22

0xA0

OUTCTL_2

R35

RW

0x23

0x20

OUTCTL_3

R36

RW

0x24

0x11

OUTDIV_2_3

R37

RW

0x25

0x00

OUTCTL_4

R38

RW

0x26

0x02

OUTDIV_4

R39

RW

0x27

0x00

OUTCTL_5

R40

RW

0x28

0x02

OUTDIV_5

R41

RW

0x29

0x00

OUTCTL_6

R42

RW

0x2A

0x05

OUTDIV_6

R43

RW

0x2B

0x50

OUTCTL_7

R44

RW

0x2C

0x62

OUTDIV_7

R45

RW

0x2D

0x0A

CMOSDIVCTRL

R46

RW

0x2E

0x00

CMOSDIV0

R47

RW

0x2F

0x00

CMOSDIV1

R48

?

0x30

0xFF

?

R49

RW

0x31

0x00

STATUS_SLEW

R50

RW

0x32

0x8A

IPCLKSEL

R51

RW

0x33

0x03

IPCLKCTL

R52

RW

0x34

0x00

PLL1_RDIV

R53

RW

0x35

0x00

PLL1_MDIV

R54

RW

0x36

0x00

PLL2_RDIV

R55

RW

0x37

0x00

PLL2_MDIV

R56

RW

0x38

0x12

PLL1_CTRL0

R57

RW

0x39

0x06

PLL1_CTRL1

R58

RW

0x3A

0x00

PLL1_NDIV_BY1

R59

RW

0x3B

0xC0

PLL1_NDIV_BY0

R60

RW

0x3C

0x00

PLL1_FRACNUM_BY2

R61

RW

0x3D

0x00

PLL1_FRACNUM_BY1

R62

RW

0x3E

0x04

PLL1_FRACNUM_BY0

R63

RW

0x3F

0x00

PLL_FRACDEN_BY2

R64

RW

0x40

0x00

PLL1_FRACDEN_BY1

R65

RW

0x41

0x0D

PLL1_FRACDEN_BY0

R66

RW

0x42

0x03

PLL1_MASHCTRL

R67

RW

0x43

0x1A

PLL1_LF_R2

R68

RW

0x44

0x04

PLL1_LF_C1

R69

RW

0x45

0x7D

PLL1_LF_R3

R70

RW

0x46

0x07

PLL1_LF_C3

R71

RW

0x47

0x06

PLL2_CTRL0

R72

RW

0x48

0x08

PLL2_CTRL1

R73

RW

0x49

0x00

PLL2_NDIV_BY1

R74

RW

0x4A

0xC6

PLL2_NDIV_BY0

R75

RW

0x4B

0x00

PLL2_FRACNUM_BY2

R76

RW

0x4C

0x00

PLL2_FRACNUM_BY1

R77

RW

0x4D

0x00

PLL2_FRACNUM_BY0

R78

RW

0x4E

0x00

PLL2_FRACDEN_BY2

R79

RW

0x4F

0x00

PLL2_FRACDEN_BY1

R80

RW

0x50

0x01

PLL2_FRACDEN_BY0

R81

RW

0x51

0x0C

PLL2_MASHCTRL

R82

RW

0x52

0x10

PLL2_LF_R2

R83

RW

0x53

0x01

PLL2_LF_C1

R84

RW

0x54

0x04

PLL2_LF_R3

R85

RW

0x55

0x07

PLL2_LF_C3

R86

RW

0x56

0x00

XO_MARGINING

R87

RW

0x57

0x00

XO_PWRCTRL

R88

RW

0x58

0x00

XO_OFFSET_GPIO5_STEP_1_BY1

R89

RW

0x59

0xDE

XO_OFFSET_GPIO5_STEP_1_BY0

R90

RW

0x5A

0x01

XO_OFFSET_GPIO5_STEP_2_BY1

R91

RW

0x5B

0x18

XO_OFFSET_GPIO5_STEP_2_BY0

R92

RW

0x5C

0x01

XO_OFFSET_GPIO5_STEP_3_BY1

R93

RW

0x5D

0x4B

XO_OFFSET_GPIO5_STEP_3_BY0

R94

RW

0x5E

0x01

XO_OFFSET_GPIO5_STEP_4_BY1

R95

RW

0x5F

0x86

XO_OFFSET_GPIO5_STEP_4_BY0

R96

RW

0x60

0x01

XO_OFFSET_GPIO5_STEP_5_BY1

R97

RW

0x61

0xBE

XO_OFFSET_GPIO5_STEP_5_BY0

R98

RW

0x62

0x01

XO_OFFSET_GPIO5_STEP_6_BY1

R99

RW

0x63

0xFE

XO_OFFSET_GPIO5_STEP_6_BY0

R100

RW

0x64

0x02

XO_OFFSET_GPIO5_STEP_7_BY1

R101

RW

0x65

0x47

XO_OFFSET_GPIO5_STEP_7_BY0

R102

RW

0x66

0x02

XO_OFFSET_GPIO5_STEP_8_BY1

R103

RW

0x67

0x9E

XO_OFFSET_GPIO5_STEP_8_BY0

R104

RW

0x68

0x00

XO_OFFSET_SW_BY1

R105

RW

0x69

0x00

XO_OFFSET_SW_BY0

R106

RW

0x6A

0x05

XO_TIMER

R107

?

0x6B

0x0F

?

R108

?

0x6C

0x0F

?

R109

?

0x6D

0x0F

?

R110

?

0x6E

0x0F

?

R111

?

0x6F

0x00

?

R112

?

0x70

0x00

?

R113

?

0x71

0x00

?

R114

?

0x72

0x00

?

R115

?

0x73

0x08

?

R116

?

0x74

0x19

?

R117

RW

0x75

0x80

PLL1_CTRL2

R118

RW

0x76

0x07

PLL1_CTRL3

R119

RW

0x77

0x05

PLL1_CALCTRL0

R120

RW

0x78

0x00

PLL1_CALCTRL1

R121

?

0x79

0x0F

?

R122

?

0x7A

0x0F

?

R123

?

0x7B

0x0F

?

R124

?

0x7C

0x0F

?

R125

?

0x7D

0x00

?

R126

?

0x7E

0x00

?

R127

?

0x7F

0x00

?

R128

?

0x80

0x00

?

R129

?

0x81

0x08

?

R130

?

0x82

0x19

?

R131

RW

0x83

0x00

PLL2_CTRL2

R132

RW

0x84

0x07

PLL2_CTRL3

R133

RW

0x85

0x05

PLL2_CALCTRL0

R134

RW

0x86

0x00

PLL2_CALCTRL1

R135

R

0x87

0x00

NVMSCRC

R136

R

0x88

0x00

NVMCNT

R137

RW

0x89

0x10

NVMCTL

R138

R

0x8A

0x00

NVMLCRC

R139

RW

0x8B

0x00

MEMADR_BY1

R140

RW

0x8C

0x00

MEMADR_BY0

R141

R

0x8D

0x00

NVMDAT

R142

RW

0x8E

0x00

RAMDAT

R143

R

0x8F

0x00

ROMDAT

R144

RW

0x90

0x00

NVMUNLK

R145

RW

0x91

0x00

REGCOMMIT_PAGE

R169

?

0xA9

0x40

?

R172

?

0xAC

0x24

?

R173

?

0xAD

0x00

?

R199

R

0xC7

XOCAPCTRL_BY1

R200

R

0xC8

XOCAPCTRL_BY0

  • Hi Rock,

    The hidden registers are the ones that we don't want users to access. They may contain trimming/slice information that should not be overwritten. If you plan to do byte write, then simply skip these registers. If block write is desired, then you need to read back the default values first and then keep those registers unchanged.

    Regards,
    Hao