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LMK04828: The reason why we use DPLL

MINKYUNG KIM
Expert 1250 points
Part Number: LMK04828
Other Parts Discussed in Thread: LMK05318

Hi team,

Would you kindly help me to understand the concept of DPLL compared to LMK04828?

This is a simplified block diagram of LMK04828 dual-loop. PLL1 is used for jitter cleaning and PLL2 for frequency synchronizing.

This is what is mentioned about DPLL in the Precision lab, and I wonder why we need this DPLL structure other than dual APLL LMK04828's structure as I attached above.

I refered to LMK05318 datasheet to understand about DPLL. And it sounds for me like DPLL is nothing more than an alternative of PLL1 in LMK04828 structure, but controlling the N divider of the cascaded APLL in more sophisticated way than they were designed in analog, thereby making more accurate(w/o phase error) and clean(w/ low in-band phase noise) reference clock to next cascaded APLL.Is this correct and Is this the point of the reason why we use DPLL?

Your kind explanation would be so helpful for me to understand the overall clock device structure for better design.

FYI, Precision lab that I refer to is .

  • 0
    TI__Expert 8585 points

    Hello Minkyung,

    A DPLL is not a one for one replacement for an APLL. A DPLL has the ability to preform hitless switching, while an APLL does not. Hitless switching allows the input clocks of a PLL to be switched with very low phase disturbance. This is possible because the phase detector in the DPLL is digital. The DPLL also minimizes the VCO drift from the XO input. This is accomplished when the DPLL is feed back into the N-divider of the APLL. Therefore, a DPLL is primarily used when we need we need both the phase and frequency of a signal to be synchronized with the input.

    As for the devices, if you need a system that provides both accurate phase and frequency, the LMK05318 would be the device to use. If you need to lower the jitter, you should use the LMK04828.

    Below is a detail explanation of how the DPLL is used in the LMK05318.

    Regards,

    Kia Rahbar

  • 0 in reply to Kia Rahbar
    Expert 1250 points

    Hello Kia, 

    Thank you for kind clarification. One thought from your comment 'DPLL is primarily used when we need we need both the phase and frequency of a signal to be synchronized with the input.' is that APLL dual loop is also capable of both phase&frequency synchronization to the input clock (e.g. LMK04828). Is it my misunderstanding?

  • 0 in reply to MINKYUNG KIM
    TI__Expert 8585 points

    Hello Minkyung,

    The APLL dual loop is also capable of phase and frequency alignment, but the phase error is not as accurate as for a DPLL. A DPLL preforms phase cancellation which decreases the phase error in comparison to an APLL.

    Regards,

    Kia Rahbar