LMK04826: analog delay jitter

Jiri Kral83

Part Number: LMK04826

Dear TI support,

is there some jitter added by not bypassing the analog delay lines on the clock outputs of the LMK0482* family? If yes, what is the additive jitter as a function of the selected analog delay? My naive expectation would be that there is some, possibly increasing with the amount of delay, but it is not discussed in the datasheet.

With best regards

- Jiri

over 4 years ago

0 Jiri Kral83 over 4 years ago

Prodigy 90 points

.. identical question for the duty cycle correction module, if it adds any jitter when not bypassed?

0 Vibhu Vanjari over 4 years ago in reply to Jiri Kral83

TI__Genius 11900 points

Hello Jiri,

The more gates added to the path the higher the jitter will be. Bypassing some of the features you mentioned such as the analog delay, dividers and DCC will definitely improve the jitter and phase noise performance. That being said we do not have any sort of characterization of jitter as a function of these different blocks being turned off. The jitter would vary based on the output frequency as well, and there may be some high order relationship between the frequency and delay. This is why it isn't discussed in the datasheet. In my experience with similar parts I've seen that by bypassing the delays you probably get back jitter in the order of 10-20 fs (12 kHz to 20 MHz integration bandwidth). That being said, I think testing specific configurations on the LMK04826BEVM would be the best next step.

Thanks,

Vibhu

0 Jiri Kral83 over 4 years ago in reply to Vibhu Vanjari

Prodigy 90 points

Hello Vibhu,

thank you for the answer. So what you say is that the jitter figures that are present in the datasheet, page 19 for example, are measured with DDC on and a maximum analog delay? Or with DDC off and no analog delay?

With best regards