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LMX2594: Setting VCO_PHASE_SYNC and INPIN_IGNORE

Part Number: LMX2594
Other Parts Discussed in Thread: TICSPRO-SW

Hi Support,

I'm trying to figure out how to set the VCO_PHASE_SYNC and INPIN_IGNORE bit fields in the LMX2594 registers.

Figure 27 in the datasheet shows two different cases of Category 1 SYNC depending on the value of the CHDIV. When CHDIV = 2, or 4, or 6, it states that SYNC mode is required but SYNC pulse is not required, does this mean in this mode VCO_PHASE_SYNC should be set to 1 and INPIN_IGNORE should be set to 1? And when CHDIV = 1, it states that SYNC mode is NOT required, meaning that VCO_PHASE_SYNC should be set to 0 and INPIN_IGNORE should be set to 1?

Any insight is highly appreciated.

Thanks,

Shant

  • Also another thing I noticed in the LMX2594_PLL.py driver code, it does not check the CHDIV value if it's greater than 6 when M is not equal to 1, in which case the flow chart in Figure 27 shows it should result in Category 4. Should I follow the flowchart recommendation or the LMX2594_PLL.py driver code in my implementation?

    Thanks,

    Shant

  • Hello Shant,

    Please follow the flowchart. The TICSPRO-SW code was not setup with this functionality. Enabling VCO_PHASE_SYNC (enabling sync mode) will automatically change the IncludedDivide and mark the N-divider in red if it breaks the minimum N-divider requirement, however I believe it will not change INPIN_IGNORE. This must be done by the user.

    For both cases of Category 1, the sync pin does not require a sync pulse. So the SYNC pin can be ignored. INPIN_IGNORE = 1.

    When CHDIV = 1 you do not need to set VCO_PHASE_SYNC, when CHDIV > 1, set VCO_PHASE_SYNC = 1.

    Thanks,

    Vibhu