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CLK synchronization output

______健
Prodigy 80 points
Other Parts Discussed in Thread: LMX2492, LMX2491, LMK04828, LMK04832, LMK04826

we have a 300MHz to 600MHz FM clk signal linear chirp in 100us，and we want a delay device that can make it delay from 0 to 3.3ns，better using voltage to control this. we find PLL that can make multichannel output of this and can adjust the phase of it. is there any PLL chip that can make it and have as more and more channel output that have adjustalbe delays ?

  • 0
    TI__Genius 11900 points

    Hello,

    LMX2491 and LMX2492 are the two devices that can generate chirps. These devices do not have any in built delay.

    We do have some buffers available with programmable delays, would this be of interest? For adjusting phase you may need to use a network synchronizer (for example LMK04828, LMK04832) in distribution mode.

    Thanks,

    Vibhu

  • 0 in reply to Vibhu Vanjari
    Prodigy 80 points

    I find this Block Diagram of LMK04826& LMK04828. if we using the VCO to generate 2GHz signal and our chirp signal(300MHz-600MHz) connect to CLKin0, can I get 14 chirp SDCLKout? the least of digital delay of SDCLKout is ?

  • 0 in reply to ______健
    TI__Guru** 110830 points

    Hi there,

    Let me clarify the requirement.

    Input clock: a chirp signal that sweep between 300MHz and 600MHz in 100µs

    Output clocks: 14 copies of the input clock with an adjustable input/output propagation delay up to 3.3ns

    Output clock format: Single-ended/CMOS/differential?

    We don't have a perfect match device for this requirement, you may try LMK01xxx series clock buffer. However, I am not sure whether it will for a chirp signal.

    The LMK048xx devices can provide more number of outputs but the analog delay is less than 1ns. You cannot use the digital delay as the device will be used in buffer mode. 

  • 0 in reply to Noel Fung
    Prodigy 80 points

    1.Output clock format: Single-ended/CMOS/differential is ok,better if have single-ended format

    2.LMK048xx's  analog delay is less than 1ns.can analog delay add the digital together？and if I give LMK048XX a chirp signal ，can the least of digital delay still be 500ps for 2GHz internal VCO？

  • 0 in reply to ______健
    TI__Genius 11900 points

    Hello,

    The LMK0482xB family does not have 14x LVCMOS outputs. It has 14 differential-only outputs.

    The LMK04832 also has 14 differential outputs and 9 of these output pairs can be configured in LVCMOS mode. In LVCMOS mode, these 9 differential outputs can be used as 18 LVCMOS single-ended outputs. CMOS outputs from the same differential output pins can be configured to be in the same phase or out of phase.

    Yes, the analog and digital delays can add, however the LMK04832 only has digital delays. The maximum digital delay can be 1023 clock cycles.

    The LMK0482xB family has both analog and digital delays, however the digital delay ca be a maximum of 32 VCO cycles.

    Thanks,

    Vibhu