CDCE72010 internal CLK Delay

Majin

Prodigy 20 points

Other Parts Discussed in Thread: CDCE72010

Hi Everyone,

If you have any information then let me know.

Question about CDCE72010 (Manual reference clock swithing):

Q1:How long about "internal delay between SmartMux from LVDS input buffer" of PRI_REF pin? Is there any deviation?

Q2:How long about "internal delay between SmartMux from LVDS input buffer" of SEC_REF pin? Is there any deviation?

Q3:How long about "working start time from REFSELCNTRL manual change"?

Thanks

over 14 years ago

0 Firoj Kabir over 14 years ago

TI__Expert 4585 points

Hi,

Unfortunately we don't have these information.

Both input paths to REFSEL MUX are identical. So, delay time is same if pre-divider is set to 1.

Thanks,

Firoj

0 Majin over 14 years ago in reply to Firoj Kabir

Prodigy 20 points

Thank you for your answer.

Since I am not sure if you understand my question Q3, let me ask my question again in another way.

When manually switching the reference clock using REF_SEL pin signal, how much does it take from one reference clock to the other after REF_SEL changes? Please let me know minimum/maximum value.

Best Regards

0 Firoj Kabir over 14 years ago in reply to Majin

TI__Expert 4585 points

Hi Majin,

Thanks for the clarification,

We don't the information you have asked for.

Thanks,

Firoj

Clock & timing

Clock & timing forum

CDCE72010 internal CLK Delay