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CDCE72010 unlock issue debug

Muralidhar Bandi
Prodigy 60 points
Other Parts Discussed in Thread: CDCE72010

Hi,

We are using CDCE72010 chip in our receiver design.We are using primary single ended input at 10dBm and using a 3.3V VCXO(LVPECL).When we load the default register settings we are seeing a PLL unlcok and we are using a 3rd order passive loopfilter.We also noticed that CP output is comming Zero volts. Please share us any debug notes/diagnosis method to overcome this issue.

Thanks/Regards,

Muralidhar

  • 0
    TI__Expert 4150 points

    Muralidhar,

    you need to make sure that the entire PLL setting including the loop filter is actually stable. You can not simply power up on the EEPROM default settings unless you have your loopfilter designed such that it cooperates with your device configuration. Please download the loop fiter tool at the following location and run the tool:

    http://e2e.ti.com/support/clocks/m/videos__files/212419.aspx

    For KVCO, enter the VCXO D/S number or calculate KVCO by: KVCO(VCXO)= fout(VCXO) [MHz] * ppm_tuning_range / dVmax(tuning_voltage_VCXO) .You should derrive a number in the order of 10kHz/V.

    For Phase Margin, choose 65. Any number between 55 and 80 should be ok.

    For Bandwidth, select your target PLL bandwidth (e.g. 100Hz).

    For T31 select 0.47.

    For Gamma select 5 (or if your external cap C2 turns out too big for your taste you can use something closer to 1).

    For CP Current you need to type in the exact current selection the CDCE72010 is set to. You can find this in the Register space of the data sheet. You can also play with this variable to change your loop bandwidth later (if you decide to change any SPI register settings).

    Configure the PLL to show the right frequencies. The input frequency will depend on your system. The VCO frequency should reflect the VCXO output frequency. You can adjust the dividers the same way the CDCE72010 is setup in your case. For example, if you have a 10MHz input, and a 100MHz VCXO, and you need 50MHz on the output, you would set 10MHz on the input, input divider (1/R) is one, feedback divider (1/N) is 10, and the output divider (1/M) is 2. Pre-scaler (1/P) is also one in this case.

    Now click on "suggest RC's". This will actually make a suggestion on good RC values for your loop filter.


    Alternatively you can now also plug in the RC loop filter values you have been using and click on "calculate Output (Using RC Input)" to see if the Phase Margin comes out stable (meaning between 55 and 80). A phase margin less than 45 is very bad, and a phase margin between 80 and 90 degree will also start to cause stability and lock problems.

     

    Hope this helps, Best regards, Fritz

  • 0
    TI__Guru* 81034 points

    Hi Muralidhar,

    One more thing to check is the VCXO termination. In the default mode the CDCE72010 has the input termination disabled, so the VCXO input must be terminated on the board.

    Best regards,

    Matt

  • 0 in reply to Matt Sunna
    TI__Expert 4150 points

    Matt is right. You can also verify if the VCXO to CDCE72010 connection is working properly by checking whether your CDCE72010 outputs actually provide the target output frequency. Even if the loop is unlocked, that VCXO will only wander off by a few ppm, so the outputs should still be very much near the target. An unterminated PECL output from the VCXO will not toggle at all, or only with a very small signal amplitude, which indicates you need 150-Ohm to GND on the VCXO P and N output.

     

  • 0 in reply to Fritz
    Prodigy 60 points

    Thanks Fritz  for the response.

    Below is the configuration we are using:

    1. Primary input at 104MHz,single ended sine wave@10dBm level.
    2. VCXO at 624MHz and LVPECL with Kvco as 9.45KHz/v.
    3. CP current 3mA

    4. PFD: 5.2MHz, 4.5ns

    5. [REGISTERS]
      REG0=683C0A40
      REG1=69800051
      REG2=69020002
      REG3=69000003
      REG4=01140004
      REG5=69400005
      REG6=69020026
      REG7=690206A7
      REG8=69020018
      REG9=69000C49
      REG10=004C013A
      REG11=8000028B
      REG12=61E09F0C
      [EVM_OUTPUTS]
      PWR_EN=1
      DEV_COMM_LED=1
      PLL_LOCK_LED=1
      CD_MODE_LED=0
      Y0_TERM=1
      Y1_TERM=0
      Y2_TERM=0
      Y3_TERM=0
      Y4_TERM=1
      Y5_TERM=0
      Y6_TERM=0
      Y7_TERM=0
      Y8_TERM=0
      Y9_TERM=1
      MODE_SEL=1
      REF_SEL=1
      AUX_SEL=0
      RESET=0
      POWER_DOWN=0

    6. Loop filter is Filter-1 used in EVM board.

  • 0 in reply to Fritz
    Prodigy 60 points

    Thanks Fritz and Matt.

    We missed this terminations in the design. We are able to lock the PLL after inclusding these terminations.

    Thanks/Regards,

    Muralidhar