Dear Ladies and Gentlemen,
we are working now on
Evalution board LM3s8962 using enet_ptpd. our experimental PTP-BASED
System is, two Evalution boards LM3s896 with enet_ptpd, the two boards
communicating each other with a normal Switch.
we want to test the Offset from Master after Sychronization. We chose
the PPS(puls per second) signal as the test Point (Pin on board is PWM2). using
oscilloscope, the Offset between two pps is 100 microseconds, this is too
big!
Sir Sergio Ortega from TI has wrote us a Email, he wrote "1. On
Fury-class MCUs (current 6000 and 8000 series), the best clock tick we
can get is 50MHz/20ns. With hardware assist, there can still be a cycle
or two of jitter (40ns) on the timestamp. So, with those two factors,
there is a +/- 60ns absolute best case timestamp."
could you help me, how can i reduce the offset.
thank you very much.
dejie Wu