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LMK04828: LMK04828 : PLL1 unlocked

Part Number: LMK04828

Hello,

We have a problem that PLL1 of LMK04828 is unlocked.

However, PLL2 is locked.

The 10MHz clock is input to CLKin1 and the 128MHz clock is output from DCLKout.

External VCXO is CVHD-950-100.000.

I've attached our schematics, TICSpro settings, and tcs files so can you tell me if there's anything wrong?

Regards.

Here is the tcs file:

[SETUP]
ADDRESS=888
CLOCK=8
DATA=4
LE=2
PART=LMK04828B
IFACE=SPI
ADDRESS_I2C=0x0

[PINS]
PINNAME00=SYNC
LOCATION00=7
PINVALUE00=False
PINNAME01=CLKin0_SEL
LOCATION01=0
PINVALUE01=False
PINNAME02=RESET
LOCATION02=3
PINVALUE02=False

[MODES]
NAME00=R0 (INIT)
VALUE00=144
NAME01=R0
VALUE01=0
NAME02=R2
VALUE02=512
NAME03=R3
VALUE03=774
NAME04=R4
VALUE04=1232
NAME05=R5
VALUE05=1371
NAME06=R6
VALUE06=1536
NAME07=R12
VALUE07=3153
NAME08=R13
VALUE08=3332
NAME09=R256
VALUE09=65556
NAME10=R257
VALUE10=65877
NAME11=R258
VALUE11=66133
NAME12=R259
VALUE12=66304
NAME13=R260
VALUE13=66592
NAME14=R261
VALUE14=66816
NAME15=R262
VALUE15=67120
NAME16=R263
VALUE16=67446
NAME17=R264
VALUE17=67604
NAME18=R265
VALUE18=67925
NAME19=R266
VALUE19=68181
NAME20=R267
VALUE20=68352
NAME21=R268
VALUE21=68640
NAME22=R269
VALUE22=68864
NAME23=R270
VALUE23=69232
NAME24=R271
VALUE24=69393
NAME25=R272
VALUE25=69640
NAME26=R273
VALUE26=69973
NAME27=R274
VALUE27=70229
NAME28=R275
VALUE28=70400
NAME29=R276
VALUE29=70656
NAME30=R277
VALUE30=70912
NAME31=R278
VALUE31=71289
NAME32=R279
VALUE32=71425
NAME33=R280
VALUE33=71688
NAME34=R281
VALUE34=72021
NAME35=R282
VALUE35=72277
NAME36=R283
VALUE36=72448
NAME37=R284
VALUE37=72704
NAME38=R285
VALUE38=72960
NAME39=R286
VALUE39=73337
NAME40=R287
VALUE40=73473
NAME41=R288
VALUE41=73748
NAME42=R289
VALUE42=74069
NAME43=R290
VALUE43=74325
NAME44=R291
VALUE44=74496
NAME45=R292
VALUE45=74752
NAME46=R293
VALUE46=75008
NAME47=R294
VALUE47=75377
NAME48=R295
VALUE48=75521
NAME49=R296
VALUE49=75784
NAME50=R297
VALUE50=76117
NAME51=R298
VALUE51=76373
NAME52=R299
VALUE52=76544
NAME53=R300
VALUE53=76800
NAME54=R301
VALUE54=77056
NAME55=R302
VALUE55=77433
NAME56=R303
VALUE56=77569
NAME57=R304
VALUE57=77826
NAME58=R305
VALUE58=78165
NAME59=R306
VALUE59=78421
NAME60=R307
VALUE60=78592
NAME61=R308
VALUE61=78848
NAME62=R309
VALUE62=79104
NAME63=R310
VALUE63=79481
NAME64=R311
VALUE64=79616
NAME65=R312
VALUE65=79876
NAME66=R313
VALUE66=80131
NAME67=R314
VALUE67=80385
NAME68=R315
VALUE68=80704
NAME69=R316
VALUE69=80896
NAME70=R317
VALUE70=81160
NAME71=R318
VALUE71=81411
NAME72=R319
VALUE72=81664
NAME73=R320
VALUE73=81923
NAME74=R321
VALUE74=82176
NAME75=R322
VALUE75=82432
NAME76=R323
VALUE76=82707
NAME77=R324
VALUE77=83199
NAME78=R325
VALUE78=83200
NAME79=R326
VALUE79=83472
NAME80=R327
VALUE80=83738
NAME81=R328
VALUE81=83979
NAME82=R329
VALUE82=84299
NAME83=R330
VALUE83=84482
NAME84=R331
VALUE84=84758
NAME85=R332
VALUE85=84992
NAME86=R333
VALUE86=85248
NAME87=R334
VALUE87=85504
NAME88=R335
VALUE88=85887
NAME89=R336
VALUE89=86019
NAME90=R337
VALUE90=86274
NAME91=R338
VALUE91=86528
NAME92=R339
VALUE92=86784
NAME93=R340
VALUE93=87041
NAME94=R341
VALUE94=87296
NAME95=R342
VALUE95=87553
NAME96=R343
VALUE96=87808
NAME97=R344
VALUE97=88214
NAME98=R345
VALUE98=88320
NAME99=R346
VALUE99=88586
NAME100=R347
VALUE100=88863
NAME101=R348
VALUE101=89120
NAME102=R349
VALUE102=89344
NAME103=R350
VALUE103=89600
NAME104=R351
VALUE104=89867
NAME105=R352
VALUE105=90112
NAME106=R353
VALUE106=90373
NAME107=R354
VALUE107=90660
NAME108=R355
VALUE108=90880
NAME109=R356
VALUE109=91136
NAME110=R357
VALUE110=91404
NAME111=R369
VALUE111=94634
NAME112=R370
VALUE112=94722
NAME113=R380
VALUE113=97301
NAME114=R381
VALUE114=97551
NAME115=R358
VALUE115=91648
NAME116=R359
VALUE116=91904
NAME117=R360
VALUE117=92224
NAME118=R361
VALUE118=92505
NAME119=R362
VALUE119=92704
NAME120=R363
VALUE120=92928
NAME121=R364
VALUE121=93184
NAME122=R365
VALUE122=93440
NAME123=R366
VALUE123=93715
NAME124=R371
VALUE124=94976
NAME125=R8189
VALUE125=2096384
NAME126=R8190
VALUE126=2096640
NAME127=R8191
VALUE127=2096979

[FLEX]
bSetFeedback_CLKin1=CLKin1 (External)
bSetFeedback_DCLKout6=DCLKout6
bSetFeedback_DCLKout8=DCLKout8
bSetFeedback_SYSREFDIV=SYSREF divider
bSetJESD204B_Continuous=Continuous
bSetJESD204B_NoJESD204B_withoutSYSREFDivider=No JESD204B
bSetJESD204B_Pulser=Pulser
bSetJESD204B_Reclocked=Reclocked
bSetJESD204B_SYSREFREQ=SYSREF Request
bSetMode_Distribution=Set Distribution
bSetMode_DualLoop=Set Dual Loop
bSetMode_DualLoop0DelayCascaded=Set Dual Loop 0-Delay Cascaded
bSetMode_DualLoop0DelayNested=Set Dual Loop 0-Delay Nested
bSetMode_SingleLoop=Set Single Loop
bSetMode_SingleLoop0Delay=Set Single Loop 0-Delay
bSet_CLKin0toOff=CLKin0 Off
bSet_CLKin0toPLL1=CLKin0 drives PLL1
bSet_CLKin0toSYSREF=CLKin0 drives SYNC/SYSREF
bSet_CLKin0toSYSREF_Direct=CLKin0 drives SYNC/SYSREF direct
bSet_CLKin1_ExternalVCO=CLKin1 drives Clock Distribution (external VCO/distribution mode)
bSet_CLKin1toOff=CLKin1 Off
bSet_CLKin1toPLL1=CLKin1 drives PLL1
bSet_CLKin2_Input=CLKin2 for PLL1
CLKDIST_FREQ=2560
CLKin0_FREQ=10
CLKin1_FREQ=10
CLKin2_FREQ=153.6
CLKin_SEL_AUTOPINSMODE=1
EXT_VCXO_FREQ=100
FB_MUX_FREQ=320
FB_MUX_FREQ_MHz=MHz
OSC_FREQ=100
OSCin_SOURCE=0
PLL1_PD_FREQ=10
PLL2_PD_FREQ=20
PLL_FBMUX_WARNING_TEXT=0
PLL_WARNING_TEXT=0
WARNING_TEXT_PLL1=
WARNING_TEXT_PLL2=
CLKDIST_FREQ=2560
SYSREF_FREQ=8
bSYNC_DIS_AllOff=All Off
bSYNC_DIS_AllOn=All On
bSYNC_DIS_CLKOff=DC Off
bSYNC_DIS_CLKOn=DC On
bSYNC_Dividers=SYNC Dividers
bSendPulsesViaSPI=Send Pulses
bSetJESD204B_Continuous=Continuous
bSetJESD204B_Pulser=Pulser
bSetJESD204B_RX_CLKin0=CLKin0
bSetJESD204B_RX_CLKin0_Bypass=CLKin0 Bypass
bSetJESD204B_RX_Ignore=None
bSetJESD204B_RX_Reclocked=Re-Clocked
bSetJESD204B_RX_SYNCpin=SYNC Pin
bSetJESD204B_SYSREFREQ=SYSREF Request
bSetSYNC_Normal=Normal
stSYSREF_CLR_WARNING=
CLKDIST_FREQ=2560
CLKout0_FREQ=128
CLKout10_FREQ=320
CLKout11_FREQ=320
CLKout12_FREQ=1280
CLKout13_FREQ=1280
CLKout1_FREQ=8
CLKout2_FREQ=128
CLKout3_FREQ=8
CLKout4_FREQ=320
CLKout5_FREQ=320
CLKout6_FREQ=320
CLKout7_FREQ=320
CLKout8_FREQ=128
CLKout9_FREQ=128
OSCout_FREQ=100
SDCLKout11_TEXT=0
SDCLKout13_TEXT=0
SDCLKout1_TEXT=0
SDCLKout3_TEXT=0
SDCLKout5_TEXT=0
SDCLKout7_TEXT=0
SDCLKout9_TEXT=0
SYSREF_FREQ=8

  • Hi there,

    Thanks for providing schematic/programming info.

    Two comments...
      - note that the TC-1-13M+ is actually a 1:1 ohms ratio balun.  So really you should use a differential termination resistor of 50 ohms instead of 100 ohms.  However, I wouldn't expect this to prevent PLL1 from locking.
      - If you used an 80 MHz VCXO, then you would be able to operate with an 80 MHz phase detector frequency resulting in improved PLL2 performance.  2560 MHz / 80 MHz = 32 (vs. 2560 MHz / 100 MHz = 25.6 which is not possible for integer N).

    Can you advise how you know PLL1 is not locked and PLL2 is locked?
      - I presume you designed your PLL1 loop filter for 1500 uA?  If you reduce this current to say 400 uA, any change?
      - To debug, please program PLL1_LD_MUX = PLL1 R/2 and PLL2_LD_MUX = PLL1 N/2.  Then you can observe the inputs to the PLL charge pump.  You should see 5 MHz clock waveforms frozen to one another (phase locked).  This won't be the case as you're not locked.
     - Could you also confirm the tuning voltage at Vtune of VCXO?

    73,
    Timothy

  • Hello user5973786,

    Are you using a 10MHz sine wave source? For a 10MHz sine wave source, you need around 12dBm signal power when going through a 1:1 balun to meet the datasheet minimum slew rate requirements. Minimum slew rate requirement is 0.15V/ns (0.075V/ns differential), and sine wave slew rate is given by SR = 2π*f*Vpk. For a 50Ω termination at 10MHz, Vpk = 0.15V/ns / (2π*10MHz) = 2.39V differential, which is just below 12dBm at each pin and at the input of the balun.

    You also have a 3dB pad (R85, R92, R95) reducing your signal amplitude, so you may want to depopulate these components and just use R92=0Ω. The pad is intended to help matching when CLKin1 is used as Fin at high frequency (>1GHz). With the pad populated, you will need around 15dBm signal power at CN6 connector to achieve 12dBm at the balun, 12dBm at the pins, and the required 0.15V/ns slew rate.

    TCS file looks okay. Assuming the "_NM" at the end of R82/C160 means these components are not populated, schematic looks okay as well.

    [edit: 1:1 balun changes impedance/power math]

    Regards,

  • Hi Derek,

    Thank you for your reply.

    I input a differential 3Vp-p clock into the pins of the LMK04828, but PLL1 did not lock.

    Is it necessary to have 4.78Vp-p(2.39V * 2) to achieve 0.15V / ns with a 10MHz sine wave?

    What is the upper limit of the LMK04828 CLKin input voltage?

    Regards,

  • Hi Timothy,

    Thank you for your comment.

    The unlock of PLL1 is known by the STATUS_LD1 pin.

    The lock of PLL2 is known by the STATUS_LD2 pin.

    I'm going to replace the loop filter gain and give it a try.

    Vtune of VCXO is 2.767V.

    Regards.

  • I wonder if you are locked, but there is some mis-reporting.  Please confirm output frequency with frequency counter.  Also, is it possible that your frequency source as more frequency error than the VCXO can pull in?

    Finally, please check the PLL1_WND_SIZE.  In some cases depending on input leakage and configuration, if this is set wrong then mis-reporting can occur.  Please increase this to 18.6 or 40 ns.

    73,
    Timothy