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LMX2582: Technical questions

Kazuki Itoh
Genius 11651 points

Part Number: LMX2582
Other Parts Discussed in Thread: LMK04828

Hi team,

1. My customer uses TICS PRO to evaluate LMX2582. TICS pro lists R68-70 which is not mentioned in the D/S. The customer doesn't need to configure these registers, correct? 

2. My customer evaluates LMX2582 + LMK04828 and struggling to reduce the spur. Any general idea to improve it?

3. Datasheet mentions multiplier low input frequency is 40MHz while the pre-R divider low output frequency is 5MHz. I don't understand this, so could you please elaborate on this? It doesn't look like bypass circuit is omitted in the functional block diagram.

Best regards,

Itoh  

  • 0
    TI__Genius 11900 points

    Hello Itoh-san,

    R69-70 do not need to be programmed, these are read only registers.

    What are these spurs, I will need more help to understand what spurs you are talking about. If these are spurs coming from the LMX2582 typically using a high slew rate, lower amplitude input may help fix spurs. If you are using a fractional PLL increasing the MASH_ORDER will decrease spur magnitudes but increase phase noise.

    Regarding the minimum frequencies, if the output of the Pre-R divider is 5 MHz, the multiplier must be set to 1. You can only use the multiplier to increase the frequency if the output of Pre-R is at least 40 MHz.

    Thanks,

    Vibhu

  • 0 in reply to Vibhu Vanjari
    TI__Genius 11651 points

    Hello Vidhu-san,

    Thank you so much for your support. I have some additional information regarding the spur. Please give me some advise.

    Please find EVM setting and results from the internal link here.

    I can see +/- 16 kHz step spur nearby the target frequency 2000.704MHz with minimum D/U = 72dB.

    My target D/U is more than 83dB.

    I don't see any spur neither from power supply nor 10MHz TCXO. So I believe the spur comes from the EVM.

    I observed some improvement by modifying Charge pump gain or MASH_ORDER, but it still doesn't meet the target D/U = 83dB.

    Also, by reducing the input level from 0dBm to -4dBm, the D/U got worse by 4dB (68dB).

    Best regards,

    Itoh 

  • 0 in reply to Kazuki Itoh
    TI__Guru** 121060 points

    Hi Itoh-san,

    According to your configuration, I expect there are multiple 16kHz spurs. These are fractional spurs, so reducing charge pump current will help. You can enable the MASH_DITHER bit to randomize the spurs. Spurs will go down, however, phase noise will degrade.

    What is the format of the 10MHz reference clock? This is a rather low reference clock frequency, if it is a sine wave or clipped sine wave, it will have negative impact to PLL noise and spurs.