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LMK04806: Check to see if the schematic design is correct

Gabriel Wang1
Genius 4715 points
Part Number: LMK04806
Other Parts Discussed in Thread: LMK00304, PLLATINUMSIM-SW

Hello, we have selected a NEW TI phase lock loop LMK04806, we would like to ask you to help check and review the schematic design (see the attachment), thank you!lmk04806 Schematic.pdf

  • 0
    TI__Guru** 107030 points

    Hi Gabriel,

    LMK00304:

    - you use CLKIN0, then you can leave CLKIN1 and OSCIN pins floating

    - REFout is not using, pull REFout_EN = 0

    Others look good.

  • 0 in reply to Noel Fung
    Expert 1470 points

    Hi Noel

    Thanks for your reply!

    Could you help us check the LMK04806 cricuits design？

  • 0 in reply to Jimmy Huang22
    TI__Mastermind 28550 points

    I suggest to put a capacitor to ground on pin 6 between IC and R186.  If the PLL_SYNC source is noisy, it could couple onto the VCO.  R186 + cap would allow option for RC filter.

    I suggest 33 pF capacitors to ground on the UWIRE lines.

    CLKOUT7 and CLKOUT9 are LVCMOS I presume.  You could operate them together on the same output as LVCMOS (Norm/Invert).  However I suspect you would like these 90 degrees apart which is not possible if sharing.  Note you can minimize crosstalk still by using the Norm/Invert output (differential) format, even if you don't use the other output.

    The loop filter on CPOUT2 appears to not be good values / not populated.  To utilize PLL2, you will want to populate PLL2 loop filter values.  Please using PLLATINUMSIM-SW to calculate a loop filter.  You could also refer to the user guide for the defalt EVM loop filter.

    For the max Icc current for FB, I don't have the data off-hand to confirm.  Did you measure using an EVM?

    For LMK00304, I notice in your type0/type1/output table, type0 should be type1 and type0 type1.  There is no need to AC coupled OSCin to ground.  You could also leave CLKin1/CLKin1 inverting open to save the 100 ohm resistors.

    73,
    Timothy

  • 0 in reply to Timothy T
    Genius 4715 points

    Thanks for your reply.

     

    According to your suggestion,I modify the cricuit design.Hope you can help me check it again.

     

    In addition, one point needs to be addressed

    1.Internal loop filter2 is used by defaul

     

  • 0 in reply to Timothy T
    Genius 4715 points

    Thanks for your reply.

     

    According to your suggestion,I modify the cricuit design.Hope you can help me check it again.

     

    In addition, one point needs to be addressed

    1.Internal loop filter2 is used by defaul

     

  • 0 in reply to Gabriel Wang1
    TI__Mastermind 33430 points

    Hello Gabriel,

    Two things:

    1. Unused outputs (CLKout5, CLKout10) should be left floating. Do not short them to GND. The unused outputs can be disabled in registers.
    2. C335, C336, and R192 must be populated and the values must be selected. The internal loop filter components comprise the third and fourth order components only, and without the first and second order components the loop will be unstable. As Timothy previously mentioned, please use PLLatinum Sim (PLLATINUMSIM-SW) to select good values for these loop filter components, or start with the suggested values in the EVM user's guide.

    Regards,