LMX2594EVM: Phase settling time

Hello Fred,

Can you try re-attaching the images, I cannot find them on your original post? Have you tried optimizing the loop filter on the EVM for fast lock time? PLLATINUMSIM-SW can be used for simulations.

Thanks,

Vibhu

Vibhu

I put the scope captures into a Word Doc this time, and inserted it as media.  Let me know if thie worked

Fred

LMX2594 scope captures.docx

Hello Fred,

Yes, I can see the pictures now. Can you double check to make sure your VCO calibration parameters are set as recommended?

FCAL_LPFD_ADJ, FCAL_HPFD_ADJ, CAL_CLK_DIV and ACAL_CMP_DLY.

You can refer to the datasheet register descriptions or TICSPRO-SW for this.

Thanks,

Vibhu

Vibhu

FCAL_LPFD_ADJ, and FCAL_HPFD_ADJ are both zero as I am using a 50 MHz reference clock.  CAL_CLK_DIV is also set to zero (divide by 1).  ACAL_CMP_DLY is set to 10.  However, since we are using full assist mode for calibration is this still a factor?

Fred

Hello Fred,

Do you see the dip and spike in on the Vtune voltage at the same instant across calibration cycles?

To help me diagnose this and identify what the problem is can you try one of the following?

1. Reduce VbiasVCO (pin3) capacitance to 1 uF (from 10 uF). This should reduce the size of the glitch
2. Follow this procedure to start full-assist calibration: (may eliminate glitch)

• Set VCO_SEL
• Set VCO_CAPCTRL
• Set R8[12] = 1
• Set VCO_DACISET
• Wait 1 ms
• Set R8[12] = 0
• Set N divider

Please let me know what happens.

Thanks,

Vibhu

Vibhu

I started to run the sequence of events that you described above.  First I wanted to set a baseline so I went through my normal sequence (see attached).  I then modified my code to perform your tuning sequence.  I was going to get that code running first and then change the VbiasVCO cap.  However, I was not able to get a lock using that sequence.  

I have some questions:

1) R8[12] is not described in the data sheet.  It shows it as always zero.  What does this do?

2)The flow chart in application note SNAA336 Page 35 (Full Assist Workflow) does not show any register writes after VCO_DACISET.  However, I was not able to get the synthesizer to lock until I wrote to register 0 (calibration bit in the OFF position).  Is my sequence incorrect?

For calibration I do the following:

1) set the channel divider/Mux as necessary

2) write to register 36 the correct N value

3) write 0x6418 to register zero

4) Delay at least one mS

5) read the VCO select, the VCO CAP, adn VCO DAC I values to a table

6) repeat for al of my 124 system frequencies

For full assist tuning the sequence is:

1) Set the channel divider, output MUX, adn reference divider

2) write to register 36 the correct N value

3) From the calibration table write the VCO select bits

4) From the calibration table write the VCO CAP value

5) From the calibration table write the VCO DAC_I value

6) Write 0x6414 for frequencies below 7500 MHz, and 2414 for higher frequencies.

Based on you reply and the flow diagram in the app note I am now uncertain that I have the correct sequence

thanks 

Fred

LMX2594 test baseline.docx

Hello Fred,

Fred Schader2 said:

1) R8[12] is not described in the data sheet.  It shows it as always zero.  What does this do?

In auto-calibration mode a high current is used to charge the VCO bias capacitor during the calibration process. This does not happen automatically in full assist mode. In most cases this isn't an issue but sometimes when we see a glitch, forcing a high current helps. This bit enables this higher current.

Fred Schader2 said:

2)The flow chart in application note SNAA336 Page 35 (Full Assist Workflow) does not show any register writes after VCO_DACISET.  However, I was not able to get the synthesizer to lock until I wrote to register 0 (calibration bit in the OFF position).  Is my sequence incorrect?

The procedure in the flow chart is correct. In the auto-calibration part of the flow chart you will set FCAL_EN = 1 to start the calibration process. As long as you don't write a 1 to FCAL_EN again the sequence should work.

I do not see an issue with your sequence, I think it should work just as well. I guess I would recommend tackling the full assist calibration issue first and leave the ramping part out for now.

Did you see improvement after testing the procedure I recommended?

On a side note, can you confirm you do not see the glitch during auto-calibration?

Thanks,

Vibhu

Vibhu

Can you clarify your answer to my second question above.? The flow chart on page 35 of snaa336 does NOT use register zero (setting the CAL enable) after the CAL table is built.  However, I have to use my step 6 above to get the synthesizer to tune and lock.  Observing on a spectrum analyzer I see that the VCO frequency is close, based on the three registers that were forced to the table values, but it is definitely not locked.  

When I then write to register zero with the CAL bit disabled I do get a phase locked condition.  

I was not able to get a lock using your sequence.  Instead I saw that Vtune was slamming against the upper and lower rail depending on which frequency I was programming.

Fred

Hi Fred,

did you set VCO_SEL_FORCE, VCO_DACISET_FORCE and VCO_CAPCTRL_FORCE = 1? They must be 1 in full assist mode. In this mode, programming the R0 register is not necessary.

Yes that is correct these bits are all set.  Since I had to use R0 to get a lock it sounds like there is some other register setting that is incorrect.  I used the TICS Pro for my register settings.  Is there an example program that shows all of the register settings in the correct sequence?

Fred

Hi Fred,

Section 3.3 of SNAA336 is an example.

Could you try the following debug?

1. lock to a frequency channel with auto-calibration

2. Read back the three VCO parameters.

3. Enable the three FORCE bits. I expect the synthesizer will unlock because you don't have the correct VCO parameters set.

4. write the three readback VCO parameters. I expect it will lock again. (This proves that no R0 programming is needed in full assist mode.)

5. change VCO_CAPCTRL to some other value, I expect it will unlock. You may also change other parameters such as PLL_N to make it unlock.

6. change VCO_CAPCTRL back to the readback value, I expect it will lock again.