Hello Experts,
My customer would like to know the PLL settings.
1. Customer would like to output CLKout2=74.25MHz. I think he should set a following register. Is it correct? Ant other register should set?
- Register: 0x2E, bit 4(PLL_DIV): "1" (divide by 2)
2. Customer would like to output CLKout4=24.576MHz. I think it is default so customer doesn't need to change any register settings, correct?
3. Customer will use CLKout2&4 and CLKout1&3 will not be used. At this time, customer would like to disable CLKout1&3. I think register 0x0A can disable output buffer for each. Is it correct? Also PLL3 can disable by register 0x31, bit 3(ICP3). Is it correct?
Best Regards,
Fujiwara