LMX2594EVM: Clock & timing forum

Christopher Beaudoin

Part Number: LMX2594EVM
Other Parts Discussed in Thread: LMX2594

I'm working on an application running at 3.2 GHz with a 10 MHz reference using TICSPRO. According to the automatically generated outputs (CHDIV etc.) the LMX2594 is operating in SYNC category 1 if I have followed the flowchart correctly. My understanding is that I must enable the VCO_PHASE_SYNC in this case but I do not need to provide a sync pulse to assert a deterministic phase on power-up. Can you confirm that this is correct?

I'm asking mainly because my test results do not demonstrate a deterministic phase relationship through power-up and I'm wondering if I have configured something incorrectly or if I have somehow misinterpreted the flow chart.

My test bench consists of sampling two 3.2 GHz signals simultaneously. The first signal is the output from the EVM (the signal from which I am looking for a deterministic phase on startup. The second signal is generated by a 3.2 frequency synthesizer that provides its reference to the EVM and if left running continously without perturbing its output in any way during the duration of the sample capture. Sample for sample, I monitor the baseband phase difference between these two signals which is very stable at the level of better than 1 degree over a period of minutes. Randomly during the capture, I power down the EVM, bring it back up, and reprogram it with TICSPRO and look to see if the phase difference continues on where it left off when the EVM was shutdown. In some cases, the EVM starts up in phase where it left off, more often though there is a significant difference in the phase difference before and after the powerdown event.

Can you offer any insight into why I am observing non-deterministic phase through a power cycle?

Chris

over 4 years ago

0 Derek Payne over 4 years ago

TI__Mastermind 33370 points

Hi Chris,

Your understanding is correct: As long as VCO_PHASE_SYNC=1, in this case, no SYNC pulse should be needed.

How much is the phase difference you're observing? Is it a consistent set of values, or seemingly random offset? There's two possibilities that come to my mind:

The included divide (common between CHDIV and NDIV) is not being properly synchronized, so there may be some phase offset at regular intervals (90°, 180°, 270°)
Powering the device down and back up again is causing some sort of temperature shift, resulting in propagation delay variation (in which case the phase of the signals should be restored after thermal equilibrium is achieved again)

Regards,

0 Christopher Beaudoin over 4 years ago in reply to Derek Payne

Prodigy 150 points

Hi Derek,

Thanks for your response. I definitely believe that I'm seeing some thermal equilibrium of the phase but that appears to thermalizes fairly quickly. In cases when the phase is restored after power down, I can see the phase stabilize to the particular over a matter of 5-10 seconds after power is restored. I believe what I am seeing are offsets that are multiples of 90deg now that you mention it. Can you tell me how I can assert synchronization between the two dividers? I don't see any other control bits aside from the VCO_PHASE_SYNC to control the SYNC state but maybe there is something else I'm overlooking? The datasheet appears to be very lean on describing the sync requirements for category 1.

Chris

0 Derek Payne over 4 years ago in reply to Christopher Beaudoin

TI__Mastermind 33370 points

Hi Chris,

If you write VCO_PHASE_SYNC=1 again a second after the device is locked, do the results look any more consistent? Writing VCO_PHASE_SYNC=1 is equivalent to generating a SYNC pulse, so perhaps synchronizing before the PLL has fully locked may cause some issues with synchronization.

Just checking: do you have the MASH seed enabled? Is there a value programmed to the MASH_SEED? These should not be required, but could be a potential confound.

Regards,

0 Christopher Beaudoin over 4 years ago in reply to Derek Payne

Prodigy 150 points

Hi Derek,

The MASH seed was enabled during programming but the combination of manually reissuing the SYNC pulse and toggling FCAL_EN appears to instill a systematic startup phase; thanks for that suggestion. Immediately following a power cycle, reprogramming, and SYNC, there is a relatively long (~10-20 seconds) period during which the phase stabilizes to its steady-state value presumably this is due to component thermalization. The following steady-state phase is typically not the phase of the output signal prior to the shutdown. My experimentation indicates that the component has to achieve thermal stasis before the SYNC is issued. Only then do I observe continuity of phase across the power cycle event. Do you know if this behavior is expected or should a SYNC issued immediately following startup (as the component is thermalizing) yield the same phase relationship? I suspect the answer is you have to or should wait until the component has thermalized but I'm wondering what TI recommends.

Thanks again,

Chris

0 Derek Payne over 4 years ago in reply to Christopher Beaudoin

TI__Mastermind 33370 points

Hi Chris,

Your results are peculiar to me, because if I take the datasheet as-written, synchronization should be deterministic from the moment of lock onward, regardless of whether the component is at thermal equilibrium. In your configuration (10MHz OSCin, 3.2GHz Fout), a divide-by-4 is included in the N-divider, and with VCO_PHASE_SYNC_EN=1 the portion of the channel divider in the loop (i.e. all of it) should be deterministically synchronized after lock every time.

My only recommendation for further testing is: Try the SYNC procedure with MASH_SEED_EN=0. There is a part in the datasheet 7.3.11 that describes "additional constraints" when MASH_SEED_EN=1 and VCO_PHASE_SYNC_EN=1, so perhaps this is one such case.

It seems like you are able to get deterministic synchronization between power cycles with the procedure you detailed, so my recommendation is to wait for thermal equilibrium because it appears to do what you need. For our part, we will check if instructions in the SYNC flowchart need to be modified for this use case.

Regards,